The foundry second source
TSMC is about three times short. Price hikes run four years. Marginal buyers look at Intel — and Samsung’s Texas fab is now a third US-footprint leg, which caps any Intel-monopoly read.
C.C. Wei said the quiet part at an industry dinner. TSMC’s capacity is “about three times short” of what customers have planned. Two-nanometer is fully booked through 2026. Three-nanometer is booked through 2028. Customers were told to expect 2nm price increases for four consecutive years starting in 2026. Arizona’s second fab does not reach 3nm volume until the second half of 2027. Kumamoto is 2028. The shortage, Wei has said, drags past 2027.
Gavin Baker’s version of the same constraint is a party TSMC is throwing for the rest of the market.
If Taiwan Semi did what Jensen wanted, I think Nvidia could sell $2 trillion of GPUs in 26 or 27… If we don't get a bubble, we need to throw a party for them because they will have single handedly prevented a bubble.
Gavin Baker
The overflow has a name. AWS signed a multi-billion-dollar 18A book. Microsoft put Maia 2 on 18A and 18A-P. Apple’s deal is still preliminary — M-class in 2027, iPhone in 2028 — with Trump personally advocating for Intel in a meeting with Tim Cook. Terafab, the Tesla/xAI/SpaceX consortium, is on 14A. Lip-Bu Tan, on Intel’s first-quarter call, added Google on a three-to-five-year long-term agreement. 18A yields were improving 7–8 percent a month, the target pulled forward to mid-2026.
Then the quarter named no one
Intel’s second-quarter print did not name an external 18A or 14A customer. External foundry revenue was about $293 million on a $5.8 billion Foundry segment that is still mostly internal. 14A still showed “two unnamed prospects,” with firm decisions slipped from the second half of 2026 into the first half of 2027. Management asserted customers. It would not name them. Internal data-center and AI silicon, up 59 percent year on year, is the demand that printed. The named external book remains asserted, not disclosed.
September 7 did not close it either. Weeks of same-day checks still found no named confirmed outside 18A or 14A high-volume order. A mid-September recap had Intel at “conviction” for securing 14A external customers — and still short of a formal engagement. SK Hynix talks about making memory chips on US soil, possibly leasing Intel’s Ohio site, sit in the same unsigned family. The plants there are delayed to 2030 and 2031. That is not a named 18A logic high-volume order. Tesla/Terafab remains an April plan, later restated as Austin R&D, not at scale. Microsoft-on-18A stays a reported Maia path; AWS a framework without disclosed volume. Fortinet on Intel 4 is the wrong node. Socionext 18A-P remains ecosystem. Internal Panther Lake volume is not an outside logic order. The next dated test is still October’s 14A PDK 0.9 plus a Tan update. Confirm is still a named outside 18A or 14A order in a filing or a call. The Q2 print still sits on an unproven foundry: $293 million external against $5.8 billion of Foundry and about $2.1 billion of operating loss.
September 15 did not convert Terafab into that named order. Musk restated it as an R&D fab at Austin’s Giga Texas for Tesla and SpaceX — equipment on order, something useful by the end of next year, not at scale. Shotwell’s crawl-walk-run line, and the packaging they already do, sit on the same podcast. The wiki files that as color on a name the bull case already carried, not a wafer start and not a reason to re-rate Intel. The 18A yield question stays open.
Honolulu published power, not yield
The June symposium was supposed to settle the comparison. It did not. Intel’s T1.2 paper and the June 16 newsroom recap said 18A-P is design-compatible with 18A and delivers more than 9 percent more performance at the same power, or more than 18 percent less power at the same performance. Thermal resistance improved 20 to 40 percent. Via resistance improved 10 to 30 percent. Risk production was underway. TSMC’s T1.5 paper, same week, compared A16 with N2P — 8 to 10 percent faster, or 15 to 20 percent less power, plus 8 to 10 percent density — with mass production slated for the fourth quarter. Same-family power and area. Not an 18A-P versus A16 yield bake-off. Neither public abstract printed a die-yield percentage.
A June 3 note in the wiki had already written that VLSI “confirmed” yield above 60 percent. The symposium ran June 14 to 18. The fetched papers do not contain that number. Leave the earlier claim standing as a pre-symposium channel. Do not overwrite it with a paper that never said it.
The quarter’s first-party language is still cost and output, not a yield table. 18A wafers ran about 25 percent above target and more than 50 percent quarter on quarter. The primary Panther Lake SKU cost fell 50 percent year to date. The June 27 10-Q still says Foundry profit was hurt by “higher-cost wafers manufactured on our Intel 18A process node.” Tan’s verbal on the call — 18A-P “around 5 percent” versus 18A — does not match the 9 / 18 paper. The wiki refuses to average them.
KeyBanc’s mid-July note now models 18A around 85 percent, TSMC N2 around 90, Samsung SF2 in the 50s. It is the same firm that supplied the mid-2025 ~55 percent figure the yield question already treats as not Intel-disclosed. There is no fetched teardown behind 85. ASML’s July 15 High-NA milestone is a layer match to the NXE platform on a subset of Panther Lake 18A layers in Oregon — tool next to tool, not Intel versus TSMC on a finished die. TSMC’s own second quarter put N2 at 3 percent of wafer revenue and declined to publish an N2 or A16 high-volume yield. The ~90 percent SRAM yield on that call is an A14 research vehicle.
Ben Thompson restated the same spine as a choice, not an accident. TSMC refuses to take the expansion risk. Hyperscalers sit on the foregone profits. “The scarcity is what ultimately saved Intel.” Risk does not disappear, he said. It just moves — “the manifestation of the risk that TSMC handed off to them.” He expects, at some point, that they will announce a major partner for the first time. A named partner is still not a purchase order. That hinge has not closed.
Wei, on TSMC’s own July call, welcomed Intel’s EMIB-T as packaging overflow. The back end, he said, is so short that he hopes a competitor takes some of the loading so TSMC’s front-end wafers can still be packaged. He also firewalled the two businesses. Packaging help is not a wedge into leading-edge foundry share. He was asked that question and answered it in the negative. That is a different article from inference beyond the GPU — wafer-scale engines and custom ASICs skip CoWoS entirely; this page is about who fabs the leading edge and where overflow packaging goes, not who serves inference without HBM stacks.
A third building in Texas
Samsung’s SF2P — a 2nm gate-all-around variant — hit 70 percent yield in January 2026, a single print that sat, on the then-available ranges, potentially above Intel 18A and toward TSMC N2. The Taylor, Texas fab was 90 percent ready on April 16, with 2nm initial manufacturing in the second quarter of 2026 and mass production by 2027. Apple executives visited the site. A visit is not an order. Apple’s primary 2nm capacity remains at TSMC.
The second-quarter print did not make foundry a disclosed profit center. Device Solutions posted 127.5 trillion won of revenue and 89.2 trillion of operating profit. Trade recaps put memory at 99.7 percent of group operating profit. Official foundry language was “improved significantly prior to incentive-related provisions,” on HBM base-die demand and US orders. A turnaround is “possible in the near term.” It is not dated. Eight-nanometer and below ran full. Advanced-node revenue was guided above 50 percent, the AI and HPC mix from the high teens to above 30. Price hikes of 10 to 15 percent on SF4, SF5, and 8nm are utilization. They are not a 2nm yield victory.
The yield series still will not sit still. January’s 70 percent SF2P remains a test-lot claim. April’s TrendForce figure, about 55 percent, is the May source of record. August Korean recaps of TrendForce now estimate about 60 percent — still below the about-70-percent bar Qualcomm and AMD are said to need. The official Q2 call gave no yield percentage. Do not average them. Qualcomm’s Snapdragon 8 Elite Gen 6 flagship is reported exclusive to TSMC N2P. Qualcomm is already an SF4 customer. AMD’s Venice EPYC ramp is official TSMC 2nm, Taiwan first, Arizona later. The May line that AMD was evaluating SF2P did not become a closed Samsung order in any fetched post-May primary.
What Samsung does have is a July 25 Broadcom memorandum. The companies “expect” more than $200 billion across memory and foundry through 2030 — 2nm and below, plus packaging. A framework. Not a disclosed wafer contract. High-NA is two tools installed, commercial volume delayed to a 1nm-class node around 2030. Intel is already using High-NA on selected 18A layers. Taylor Fab 1 operations in 2026, a gradual 2nm ramp; Fab 2 groundbreaking late 2026, mass production 2030. After Q2 the wiki’s read is that Samsung is a more credible 4nm, HBM-base-die, utilization third. It is not yet a co-equal leading-edge alternative that would split Apple, Qualcomm flagship, or AMD Venice volume. The Intel-as-alternative thesis is resized at the margin. It is not falsified.
The US-footprint set is now three buildings: TSMC Arizona (3nm in the second half of 2027), Intel Fab 52, and Samsung Taylor. Order flow may split rather than concentrate on Intel. Baker’s falsification is about discipline, not yield: one of Intel or Samsung will break, and then everyone else will. The picks-and-shovels names — ASML, Applied, KLA, Lam — take capex from all three buildouts. That book is the one least hostage to which logo wins the wafer.