Autoresearch: Section 232 semiconductor tariffs Phase 2 — May 2026 update

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Summary

Section 232 semiconductor tariffs are bifurcated: Phase 1 (25% tariff on narrow AI chip category, effective January 15, 2026) is already law; Phase 2 (broader tariffs + tariff-offset program for US fab investors) is formally planned but awaiting two triggers — the April 14, 2026 USTR/Commerce negotiation update (already past, no public announcement) and a July 1, 2026 Commerce data-center market report that will drive the President's Phase 2 decision. The tariff-offset program, which gives preferential treatment to companies investing in US semiconductor production, remains unspecified in its mechanics. Crucially, the CHIPS Act Section 48D investment tax credit was expanded from 25% to 35% by the "One Big Beautiful Bill Act" (July 4, 2025) and construction deadline extended to December 31, 2026 — but the Semiconductor Industry Association is now pressing Congress for a further extension beyond 2026, anchoring $640B in announced domestic fab investment. These two incentive structures (Section 232 tariff stick + 48D tax credit carrot) are converging into a dual-lever US industrial policy for onshoring semiconductor production.

Findings

Phase 1: what is in effect now

Proclamation 11002 (January 14, 2026) imposed a 25% ad valorem tariff on advanced semiconductors meeting defined Tensor Processing Performance (TPP) and DRAM bandwidth thresholds, effective January 15, 2026 (White House, EY Global Tax News, White & Case).

Key scope details:

• Targets: NVIDIA H200, AMD MI325X, and chips meeting the same TPP/DRAM thresholds. Advanced AI accelerators, not commodity logic chips.
• Exemption: US data-center supply chain imports are exempted — meaning chips imported for immediate use in US data-center builds appear to have a carve-out, though interpretation is still in flux per customs brokers (Fleischer CHB, Z2Data).
• Semiconductor manufacturing equipment: Also in scope per the proclamation title, though Phase 1 focused on chips; equipment tariffs may be part of Phase 2 structure.

The tariff is structured as a pressure mechanism — not a permanent revenue tool. The goal is to accelerate US fab investment by making imported AI chips more expensive than chips produced domestically.

Phase 2: the pending escalation

Per the proclamation itself (Cassidy Levy Kent, Baker Donelson):

• Phase 2 structure: Broader tariffs covering a wider product set, at a rate described as "significant." Accompanied by a tariff-offset program allowing companies investing in US semiconductor production or the US semiconductor supply chain to receive preferential (lower) tariff treatment.
• April 14 trigger: USTR + Commerce were required to deliver a status update on semiconductor trade negotiations to the President by April 14, 2026. This deadline has passed — no public announcement of what was delivered or any resulting action. Taiwan negotiations are ongoing.
• July 1 trigger: Commerce must deliver a full market update on semiconductors used in US data centers by July 1, 2026. The President then decides whether to modify (or accelerate) the tariff structure. This is the next hard deadline — 43 days from today.

The tariff-offset program mechanics have not been publicly specified. It is described in the proclamation as forthcoming but neither the eligibility criteria, offset rates, nor application process have been announced (GingerControl, SmarTrade).

Taiwan dimension: USTR and Commerce are negotiating jointly with Taiwan as a "key country in the semiconductor supply chain." A February 2026 summary noted a "Taiwan deal signal" alongside the BIS rule and Section 232 actions (Global Policy Watch) — suggesting a bilateral arrangement is in progress that could affect Phase 2 application to TSMC-Taiwan chips specifically.

CHIPS Act 48D: expanded but deadline pressure remains

The CHIPS Act Section 48D Advanced Manufacturing Investment Credit (AMIC) — the investment tax credit for US semiconductor fabs — has already been strengthened:

• One Big Beautiful Bill Act (signed July 4, 2025): Expanded 48D from 25% → 35% and extended the construction-start deadline to December 31, 2026 (Pillsbury, TechTimes).
• Industry concern: The December 31, 2026 construction-start deadline is now only ~7 months away. New fabs that break ground after that date get no credit. The Semiconductor Industry Association (SIA) + 17 allied trade groups sent a formal letter to Congress on May 12, 2026 urging a further extension beyond 2026 (TechTimes).
• Scale: $640B in announced domestic chip investment is anchored to the credit. TSMC Arizona phases 2-3, Intel Ohio/Arizona expansions, Samsung Taylor TX, Micron Idaho — all benefit.
• STAR Act: Industry is also pushing to expand 48D to cover semiconductor design and R&D (not just physical fab construction) — not yet passed.

Key convergence: The July 1 Phase 2 decision + December 31 48D deadline create simultaneous policy uncertainty for any company considering breaking ground on a new US fab in H2 2026. A company that waits for Phase 2 clarity before committing risks missing the 48D credit window.

Investment positioning: who benefits from the tariff stick + credit carrot

The dual policy creates a clear beneficiary set:

• US domestic fab investors: Any company with announced US fab investment (Intel, TSMC Arizona, Samsung Taylor, Micron) benefits from the tariff-offset program if it materializes, and has already benefited from the expanded 48D credit.
• TSMC Arizona specifically: Chips produced in TSMC Arizona are exempt from the 25% tariff; chips produced in TSMC Taiwan are subject to it. This creates a built-in price advantage for Arizona-produced chips vs Taiwan-sourced equivalents — a structural demand pull for TSMC US capacity.
• Intel: If the tariff-offset program applies to full-stack US chip producers (design + manufacture), Intel's domestic production model is the cleanest beneficiary. Intel's current financial stress means the offset program (reduced tariff burden on sales of domestically-produced chips?) could be a near-term revenue lever.
• Equipment makers: If Phase 2 includes semiconductor manufacturing equipment tariffs, ASML (European) imports face cost pressure; but domestic capital equipment spending in the US (KLA, Lam, Applied Materials) benefits from higher-priced alternatives.
• Hyperscalers importing AI chips: Cost-pressured by Phase 1 tariff. If the US data-center exemption is narrowly interpreted, NVIDIA/AMD imports for hyperscaler customers face 25% markup — effectively a tax on AI buildout that creates a pull toward US-produced AI chips.

Contradictions and open questions

• April 14 silence: The USTR/Commerce negotiation update was due April 14. Zero public reporting on what was delivered. Either it was classified, produced no action, or triggered something not yet announced. This is the biggest information gap — it may have set the Phase 2 parameters already.
• Tariff-offset program mechanics: The most material unknown. A 20-25% tariff offset for US fab investors is qualitatively different from a 5% offset. The rate and eligibility criteria will determine whether the program is a meaningful incentive or symbolic.
• Taiwan deal shape: If the US-Taiwan semiconductor deal grants TSMC-Taiwan preferential treatment under Phase 2, the "TSMC Arizona vs Taiwan" price differential could narrow — moderating the pull toward Arizona capacity.
• Data-center import exemption scope: The Phase 1 exemption for US data-center supply chain is not well-defined in public sources. If narrowly interpreted, hyperscaler imports are subject to the 25% tariff now. If broadly interpreted, the Phase 1 tariff primarily hits distributors/resellers and smaller importers.
• 48D construction deadline extension: Will Congress pass an extension before December 31, 2026? The SIA letter (May 12) is advocacy pressure; there's no legislative vehicle identified yet to carry it.
• Phase 2 rate: "Significant" tariff rate — does this mean 25% matching Phase 1, or escalated to 50%? The policy precedent in other Section 232 actions (steel 25%, aluminum 10%, now adjusted upward) suggests 25-50% is the likely range.

Provenance

Rounds run: 3 of 3

Sub-questions by round:

Round 1 (broad survey):

1. What is the current status of Section 232 semiconductor tariff Phase 2 — any announcements since January 2026?
2. What are the mechanics of the tariff-offset program and which companies benefit?

Round 2 (drill-down):

1. Any May 2026 Commerce/USTR Phase 2 announcement — targeting the April 14 deadline follow-through
2. CHIPS Act 48D extension status — targeting the parallel incentive structure and December 2026 deadline pressure

Round 3 (resolve remaining uncertainty):

1. April 14 negotiation update and Taiwan deal shape — targeted the biggest information gap

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Tools used: WebSearch (3 rounds, 5 queries). Generated: 2026-05-19