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2026 08 25 Conference Vlsi Symposium 2026 Program
Official program extract from https://www.vlsisymposium.org/wp-content/uploads/2026/05/VLSI26_Program_Finalv2.pdf. 313 new papers/sessions since last state.
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Summary
Official program extract from https://www.vlsisymposium.org/wp-content/uploads/2026/05/VLSI26_Program_Finalv2.pdf. 313 new papers/sessions since last state. Official page only — titles and authors as listed on the program; no secondary blog coverage.
Program
- P1.1 8:35 AM
https://www.vlsisymposium.org/wp-content/uploads/2026/05/VLSI26_Program_Finalv2.pdf - P1.2 9:15 AM
https://www.vlsisymposium.org/wp-content/uploads/2026/05/VLSI26_Program_Finalv2.pdf - Session C1: High-Frequency Arrays for 6G and SATCOM
https://www.vlsisymposium.org/wp-content/uploads/2026/05/VLSI26_Program_Finalv2.pdf - C1.1 A 129-Gb/s CMOS W-band Polarization-Modulated Active Relay Transceiver Supporting Concurrent
Session: Session C1: High-Frequency Arrays for 6G and SATCOM
https://www.vlsisymposium.org/wp-content/uploads/2026/05/VLSI26_Program_Finalv2.pdf - C1.2 A 240–270 GHz 4x4 Bi-Directional Phased-Array Transceiver with On-Chip Half-Wavelength-Spaced
Session: Session C1: High-Frequency Arrays for 6G and SATCOM
https://www.vlsisymposium.org/wp-content/uploads/2026/05/VLSI26_Program_Finalv2.pdf - C1.3 A Ka-Band Time-Division Multi-Stream Phased-Array Transmitter with Built-in Spatial Notch Generation
Session: Session C1: High-Frequency Arrays for 6G and SATCOM
https://www.vlsisymposium.org/wp-content/uploads/2026/05/VLSI26_Program_Finalv2.pdf - C1.4 An Ultra-Compact 4-Element 4-Beam Q-band Multibeamformer IC with IQ Pre-weighted Phase Shifter
Session: Session C1: High-Frequency Arrays for 6G and SATCOM
https://www.vlsisymposium.org/wp-content/uploads/2026/05/VLSI26_Program_Finalv2.pdf - C1.5 A 144Gbps D-Band Dual-Polarized MIMO High-Density Phased-Array Transceiver in 65nm CMOS for 6G
Session: Session C1: High-Frequency Arrays for 6G and SATCOM
https://www.vlsisymposium.org/wp-content/uploads/2026/05/VLSI26_Program_Finalv2.pdf - Session C2: High-Voltage-Ratio and Scalable Power Delivery
https://www.vlsisymposium.org/wp-content/uploads/2026/05/VLSI26_Program_Finalv2.pdf - C2.1 A Monolithic 20W/mm2 4.8V Input 94.8% Peak Efficiency 2-1 Switched Capacitor Voltage Regulator as
Session: Session C2: High-Voltage-Ratio and Scalable Power Delivery
https://www.vlsisymposium.org/wp-content/uploads/2026/05/VLSI26_Program_Finalv2.pdf - C2.2 A 2D-Extendable 48V-1V Ladder-Series-Capacitor Buck Converter for Computing Power Delivery, Zhiguo
Session: Session C2: High-Voltage-Ratio and Scalable Power Delivery
https://www.vlsisymposium.org/wp-content/uploads/2026/05/VLSI26_Program_Finalv2.pdf - C2.3 A 12V-to-1V Scalable 2N-Phase Buck Converter using 0V-Stress Balancer with Shortest IL Balancing
Session: Session C2: High-Voltage-Ratio and Scalable Power Delivery
https://www.vlsisymposium.org/wp-content/uploads/2026/05/VLSI26_Program_Finalv2.pdf - C2.4 A 48V-5V Coupled-Inductor Middle-Switched-Capacitor Hybrid GaN Converter Achieving 156µH
Session: Session C2: High-Voltage-Ratio and Scalable Power Delivery
https://www.vlsisymposium.org/wp-content/uploads/2026/05/VLSI26_Program_Finalv2.pdf - C2.5 A 0.5W/mm2-Power-Density, 91.6%-Peak-Efficiency, Resonant Dual-Path Interleaved DC-DC
Session: Session C2: High-Voltage-Ratio and Scalable Power Delivery
https://www.vlsisymposium.org/wp-content/uploads/2026/05/VLSI26_Program_Finalv2.pdf - Session C3: Accelerators: Spatial and Immersive Visual Computing
https://www.vlsisymposium.org/wp-content/uploads/2026/05/VLSI26_Program_Finalv2.pdf - C3.1 Gleanmer: A 6 mW SoC for Real-Time 3D Gaussian Occupancy Mapping, Zih-Sing Fu1, Peter Zhi Xuan Li1,
Session: Session C3: Accelerators: Spatial and Immersive Visual Computing
https://www.vlsisymposium.org/wp-content/uploads/2026/05/VLSI26_Program_Finalv2.pdf - C3.2 NOVA: A 5.3mJ/frame Fully Integrated Neural Video SoC with Content-Adaptive Architecture for 4K
Session: Session C3: Accelerators: Spatial and Immersive Visual Computing
https://www.vlsisymposium.org/wp-content/uploads/2026/05/VLSI26_Program_Finalv2.pdf - C3.3 SR-VLNA: A 5.0-23.9 mJ/meter Spatial Reasoning-based Vision Language Navigation Accelerator for
Session: Session C3: Accelerators: Spatial and Immersive Visual Computing
https://www.vlsisymposium.org/wp-content/uploads/2026/05/VLSI26_Program_Finalv2.pdf - C3.4 Event-Gaze: A 28nm 441μs-Latency 12.88mW SoC for Sparse-Event-Based Dynamic Eye Tracking and
Session: Session C3: Accelerators: Spatial and Immersive Visual Computing
https://www.vlsisymposium.org/wp-content/uploads/2026/05/VLSI26_Program_Finalv2.pdf - C3.5 Uni4D: A 12nm 0.16mJ/Frame 4D Gaussian Spatial Video Rendering Processor with Unified Deformation
Session: Session C3: Accelerators: Spatial and Immersive Visual Computing
https://www.vlsisymposium.org/wp-content/uploads/2026/05/VLSI26_Program_Finalv2.pdf - Session T1: T1 - Technology Highlights
https://www.vlsisymposium.org/wp-content/uploads/2026/05/VLSI26_Program_Finalv2.pdf - T1.1 First demonstration of 3D Stacked FETs at Gate Pitch of 42 nm Featuring Triple Stacked Nanosheet
Session: Session T1: T1 - Technology Highlights
https://www.vlsisymposium.org/wp-content/uploads/2026/05/VLSI26_Program_Finalv2.pdf - T1.2 Intel 18A-P CMOS Technology Enhancement Featuring Advanced RibbonFET (GAA) Transistors and
Session: Session T1: T1 - Technology Highlights
https://www.vlsisymposium.org/wp-content/uploads/2026/05/VLSI26_Program_Finalv2.pdf - T1.3 First EUV-enabled integration route for 50 nm pitch N and PMOS transistors with 2D materials channel
Session: Session T1: T1 - Technology Highlights
https://www.vlsisymposium.org/wp-content/uploads/2026/05/VLSI26_Program_Finalv2.pdf - T1.4 A Multi-Stacked Cell Array Architecture with Wafer-to-Wafer Cu Direct Bonding for Ultra-High-Density
Session: Session T1: T1 - Technology Highlights
https://www.vlsisymposium.org/wp-content/uploads/2026/05/VLSI26_Program_Finalv2.pdf - T1.5 A16 Angstrom-class CMOS Technology featuring Enhanced Nanosheet Transistors with Super-Power
Session: Session T1: T1 - Technology Highlights
https://www.vlsisymposium.org/wp-content/uploads/2026/05/VLSI26_Program_Finalv2.pdf - Session C4: Advanced High-Frequency Synthesizers
https://www.vlsisymposium.org/wp-content/uploads/2026/05/VLSI26_Program_Finalv2.pdf - C4.1 A 209~245GHz CMOS Spectroscopic Transmitter with DTC-Based 4FSK Baseline Elimination and PhaseOffset Calibrated SSPLL for Chip-Scale Molecular Clocks, Geyu Qiang1, Xiao Luo1, Xinyang Chen1, Chang Liu2,
Session: Session C4: Advanced High-Frequency Synthesizers
https://www.vlsisymposium.org/wp-content/uploads/2026/05/VLSI26_Program_Finalv2.pdf - C4.2 A 45.3-to-53.9-GHz Circular-Dual-Core Series-Resonance-Harmonic-Extraction VCO Featuring
Session: Session C4: Advanced High-Frequency Synthesizers
https://www.vlsisymposium.org/wp-content/uploads/2026/05/VLSI26_Program_Finalv2.pdf - C4.3 A 54-to-60GHz Cascaded PLL Featuring Implicit Frequency Doubling and Harmonic-Mixing Phase
Session: Session C4: Advanced High-Frequency Synthesizers
https://www.vlsisymposium.org/wp-content/uploads/2026/05/VLSI26_Program_Finalv2.pdf - C4.4 A 28-GHz Quadrature LO-Phase-Shifting Digital Wave-Locked Loop (WLL) Achieving 57.2-fsrms Jitter,
Session: Session C4: Advanced High-Frequency Synthesizers
https://www.vlsisymposium.org/wp-content/uploads/2026/05/VLSI26_Program_Finalv2.pdf - Session C5: Isolated and Multi-Domain Power Conversion
https://www.vlsisymposium.org/wp-content/uploads/2026/05/VLSI26_Program_Finalv2.pdf - C5.1 4.5-W 5-V-Input DC-DC Converter with Six Isolated 15-V Outputs Achieving 175-kV/µs CMTI Without
Session: Session C5: Isolated and Multi-Domain Power Conversion
https://www.vlsisymposium.org/wp-content/uploads/2026/05/VLSI26_Program_Finalv2.pdf - C5.2 Class-D LC Oscillator-Based Capacitively Isolated DC-DC Converters with False-Mode Prevention
Session: Session C5: Isolated and Multi-Domain Power Conversion
https://www.vlsisymposium.org/wp-content/uploads/2026/05/VLSI26_Program_Finalv2.pdf - C5.3 A 6.8W 91.3%-Peak-Efficiency Coupled Micro-Inductor-Based Bidirectional Isolated Converter with TriState Magnetic Charging for Battery Active Cell Equalization, Bin Chen1, Yike Fang1, Tao Zhu1, Yi Fang1, Yuhang
Session: Session C5: Isolated and Multi-Domain Power Conversion
https://www.vlsisymposium.org/wp-content/uploads/2026/05/VLSI26_Program_Finalv2.pdf - C5.4 VSIMO: A DC-DC SIMO-based Current Mismatch Compensator Supporting Per-Output Bidirectional
Session: Session C5: Isolated and Multi-Domain Power Conversion
https://www.vlsisymposium.org/wp-content/uploads/2026/05/VLSI26_Program_Finalv2.pdf - Session C6: Intelligent Vision and Perception Sensors
https://www.vlsisymposium.org/wp-content/uploads/2026/05/VLSI26_Program_Finalv2.pdf - C6.1 A Hybrid Processing-in-Sensor Architecture with a Computational Mosaic Array and ResidualEnhanced Analog Skip Connections for Robust Color Vision, Hyoungjun Kim1, Ethan Chen1, Vanessa Chen1
Session: Session C6: Intelligent Vision and Perception Sensors
https://www.vlsisymposium.org/wp-content/uploads/2026/05/VLSI26_Program_Finalv2.pdf - C6.2 A 50M pixels 1.22μm Pitch Pixel Image Sensor with 100dB Single Exposure Dynamic Range by Triple
Session: Session C6: Intelligent Vision and Perception Sensors
https://www.vlsisymposium.org/wp-content/uploads/2026/05/VLSI26_Program_Finalv2.pdf - C6.3 A 3.86 TOPS/W TTFS-Based Neuromorphic Image Sensor Featuring Clocked-Recharging SPAD Pixels
Session: Session C6: Intelligent Vision and Perception Sensors
https://www.vlsisymposium.org/wp-content/uploads/2026/05/VLSI26_Program_Finalv2.pdf - C6.4 All-Digital Event-based Vision Sensor with Scene Adaptive Power-Saving Pixels and Three-Layer Neural
Session: Session C6: Intelligent Vision and Perception Sensors
https://www.vlsisymposium.org/wp-content/uploads/2026/05/VLSI26_Program_Finalv2.pdf - Session C7: Accelerators: Generative Models and Specialized Decoding
https://www.vlsisymposium.org/wp-content/uploads/2026/05/VLSI26_Program_Finalv2.pdf - C7.1 Silicon-Oracle (Soracle): A Multi-Modal Autoregressive Model Accelerator for Context-Aware
Session: Session C7: Accelerators: Generative Models and Specialized Decoding
https://www.vlsisymposium.org/wp-content/uploads/2026/05/VLSI26_Program_Finalv2.pdf - C7.2 SPECTRA: An Asymmetric-Precision Speculative Decoding LLM Accelerator with Product Quantization
Session: Session C7: Accelerators: Generative Models and Specialized Decoding
https://www.vlsisymposium.org/wp-content/uploads/2026/05/VLSI26_Program_Finalv2.pdf - C7.3 A Full-MWPM Surface Code Decoder with On-the-Fly Weight Computation and Cross-Platform
Session: Session C7: Accelerators: Generative Models and Specialized Decoding
https://www.vlsisymposium.org/wp-content/uploads/2026/05/VLSI26_Program_Finalv2.pdf - C7.4 A 122.2μJ/Token Reasoning LLM Accelerator with Reinforcement Fine-Tune Featuring Two-Level KVCache Compression and Spike-Driven Predictive Update, Mingxuan Li1, Wenjie Ren1, Zhuolin Li1, Le Ye1, Tianyu
Session: Session C7: Accelerators: Generative Models and Specialized Decoding
https://www.vlsisymposium.org/wp-content/uploads/2026/05/VLSI26_Program_Finalv2.pdf - Session JFS1: Quantum Computing & Cryo-CMOS
https://www.vlsisymposium.org/wp-content/uploads/2026/05/VLSI26_Program_Finalv2.pdf - JFS1.1 Developing a Quantum Computer with Electrically Driven Spin Qubits, Takashi Nakajima1, Kenta
Session: Session JFS1: Quantum Computing & Cryo-CMOS
https://www.vlsisymposium.org/wp-content/uploads/2026/05/VLSI26_Program_Finalv2.pdf - JFS1.2 Detecting Quantum Errors with Hardware-efficient Checks, Ali Javadi-Abhari1, Simon Martiel2
Session: Session JFS1: Quantum Computing & Cryo-CMOS
https://www.vlsisymposium.org/wp-content/uploads/2026/05/VLSI26_Program_Finalv2.pdf - JFS1.3 A Cryo-CMOS Fully-Integrated Superconducting Qubit Reflectometry Readout IC with FCNN-Based
Session: Session JFS1: Quantum Computing & Cryo-CMOS
https://www.vlsisymposium.org/wp-content/uploads/2026/05/VLSI26_Program_Finalv2.pdf - JFS1.4 Cryo-CMOS sub-1K 16nm FinFET DAC for Fast Two-Qubit Gates in Spin Qubits, Ilker Polat1, Ramon W.J.
Session: Session JFS1: Quantum Computing & Cryo-CMOS
https://www.vlsisymposium.org/wp-content/uploads/2026/05/VLSI26_Program_Finalv2.pdf - Session T2: Backside Power Delivery
https://www.vlsisymposium.org/wp-content/uploads/2026/05/VLSI26_Program_Finalv2.pdf - T2.1 Improved Backside Contacting for CFET, Cassie Sheng1, Steven Demuynck1, Dmitry Batuk1, Jishnu
Session: Session T2: Backside Power Delivery
https://www.vlsisymposium.org/wp-content/uploads/2026/05/VLSI26_Program_Finalv2.pdf - T2.2 High-Performance 2nm GAA Standard Cell Architecture Exploiting Backside Power Delivery via Dynamic
Session: Session T2: Backside Power Delivery
https://www.vlsisymposium.org/wp-content/uploads/2026/05/VLSI26_Program_Finalv2.pdf - T2.3 CPU Cores in GAA with Backside Power: Silicon-Validated Design Insights, Manjunath Shamanna1, M
Session: Session T2: Backside Power Delivery
https://www.vlsisymposium.org/wp-content/uploads/2026/05/VLSI26_Program_Finalv2.pdf - T2.4 Backside Contact Resistivity Reduction for Nanosheet Technologies Beyond 2nm by Backside
Session: Session T2: Backside Power Delivery
https://www.vlsisymposium.org/wp-content/uploads/2026/05/VLSI26_Program_Finalv2.pdf - Session C8: Compute-In-Memory
https://www.vlsisymposium.org/wp-content/uploads/2026/05/VLSI26_Program_Finalv2.pdf - C8.1 A 2nm 234.4 TOPS/W and 511.9 TOPS/mm2 Digital Computing-in-Memory Compiler with Multiple MAC
Session: Session C8: Compute-In-Memory
https://www.vlsisymposium.org/wp-content/uploads/2026/05/VLSI26_Program_Finalv2.pdf - C8.2 A 0.0257 mm², 1.16 µW, Mask-Efficient KWS SoC with Hybrid Cap-ROM-IMC/SRAM-NMC and Transfer
Session: Session C8: Compute-In-Memory
https://www.vlsisymposium.org/wp-content/uploads/2026/05/VLSI26_Program_Finalv2.pdf - C8.3 A 28nm 44.15TFLOPS/W and 1.57TFLOPS/mm2 Joint-Alignment Floating-point CIM Macro with ISO26262
Session: Session C8: Compute-In-Memory
https://www.vlsisymposium.org/wp-content/uploads/2026/05/VLSI26_Program_Finalv2.pdf - C8.4 A 28nm CMOS-Integrated VCMA-MTJ Dual-Function Macro for Deterministic In-Memory Computing
Session: Session C8: Compute-In-Memory
https://www.vlsisymposium.org/wp-content/uploads/2026/05/VLSI26_Program_Finalv2.pdf - C8.5 A 40nm 24.85-to-80.59 TFLOPS/W FP8 Computing-in-Memory Macro with Outlier-Aware HierarchicalAlignment for Edge Transformers, Zhiwei Zhou1, Tong Hu1, Jia Chen1, Jiancong Li2, YuYang Fu1, Yi Li1, Xiangshui
Session: Session C8: Compute-In-Memory
https://www.vlsisymposium.org/wp-content/uploads/2026/05/VLSI26_Program_Finalv2.pdf - Session C9: Neural-Interface Processors & SoCs
https://www.vlsisymposium.org/wp-content/uploads/2026/05/VLSI26_Program_Finalv2.pdf - C9.1 A 64-Channel, Low-Power End-to-End Transformer-Based BCI SoC for Efficient Motion Intention
Session: Session C9: Neural-Interface Processors & SoCs
https://www.vlsisymposium.org/wp-content/uploads/2026/05/VLSI26_Program_Finalv2.pdf - C9.2 An In-Ear Sleep Modulation SoC Featuring a CNN–LSTM Accelerator with Long-Kernel Memory Reuse
Session: Session C9: Neural-Interface Processors & SoCs
https://www.vlsisymposium.org/wp-content/uploads/2026/05/VLSI26_Program_Finalv2.pdf - C9.3 TARNA: A 1.18-µW/Channel Topology-Aware Residual Recurrent CIM Processor for Zero-Shot Seizure
Session: Session C9: Neural-Interface Processors & SoCs
https://www.vlsisymposium.org/wp-content/uploads/2026/05/VLSI26_Program_Finalv2.pdf - C9.4 A 16-Channel Neural Recording IC with Spike-Driven Adaptive-Basis Compressive Sensing, Sanghoon
Session: Session C9: Neural-Interface Processors & SoCs
https://www.vlsisymposium.org/wp-content/uploads/2026/05/VLSI26_Program_Finalv2.pdf - Session C10: Building Blocks for Multimodal Sensors
https://www.vlsisymposium.org/wp-content/uploads/2026/05/VLSI26_Program_Finalv2.pdf - C10.1 A 75nW BJT-based Temperature Sensor with ±0.1 °C Inaccuracy from -40°C to 85°C, Jida Peng1, Nandor
Session: Session C10: Building Blocks for Multimodal Sensors
https://www.vlsisymposium.org/wp-content/uploads/2026/05/VLSI26_Program_Finalv2.pdf - C10.2 A MEMS-Based Throughflow Multimodal Sensor Interface IC for Real-Time Fluid Parameter
Session: Session C10: Building Blocks for Multimodal Sensors
https://www.vlsisymposium.org/wp-content/uploads/2026/05/VLSI26_Program_Finalv2.pdf - C10.3 A SPAD-Based iToF Flash LiDAR Sensor with a Coarse-Fine Operation Scheme Robust Against Strong
Session: Session C10: Building Blocks for Multimodal Sensors
https://www.vlsisymposium.org/wp-content/uploads/2026/05/VLSI26_Program_Finalv2.pdf - C10.4 A 3nm Variation-Tolerant On-Die Current Sensor for Power-Limits Management, Fikre Gebreyohannes1,
Session: Session C10: Building Blocks for Multimodal Sensors
https://www.vlsisymposium.org/wp-content/uploads/2026/05/VLSI26_Program_Finalv2.pdf - C10.5 Unified Digital Thermal-Voltage Sensor for Thermal Management in Intel 18A/Intel 3, Shanshan Xie1,
Session: Session C10: Building Blocks for Multimodal Sensors
https://www.vlsisymposium.org/wp-content/uploads/2026/05/VLSI26_Program_Finalv2.pdf - Session T3: 2D Channel Materials
https://www.vlsisymposium.org/wp-content/uploads/2026/05/VLSI26_Program_Finalv2.pdf - T3.1 Scaling VDD for P-type 2D-Material Channel Transistor: What Non-Idealities Are Still to Be Solved, ChaoChing Cheng1, Ang-Sheng Chou1, Edward Chen1, Ming-Yang Li1, Yu-Wei Hsu1,2, Chia-Chin Cheng1, Seong Rae Cho3,
Session: Session T3: 2D Channel Materials
https://www.vlsisymposium.org/wp-content/uploads/2026/05/VLSI26_Program_Finalv2.pdf - T3.2 Enhancement-Mode Monolayer WSe2 pFETs with Record ION/IOFF at Contact Length of 30nm, Yuan-Chun
Session: Session T3: 2D Channel Materials
https://www.vlsisymposium.org/wp-content/uploads/2026/05/VLSI26_Program_Finalv2.pdf - T3.3 Performance Demonstration of Monolayer MoS2 Transistors at Cryogenic Temperatures Down to 6 K for
Session: Session T3: 2D Channel Materials
https://www.vlsisymposium.org/wp-content/uploads/2026/05/VLSI26_Program_Finalv2.pdf - T3.4 Atomic Layer Deposition of Epitaxial Semimetal Contacts for 2D Transistors, Huije Ryu1, Jongwon Lee2,
Session: Session T3: 2D Channel Materials
https://www.vlsisymposium.org/wp-content/uploads/2026/05/VLSI26_Program_Finalv2.pdf - T3.5 Wafer-scale Two-channel Monolayer-MoS2 Nanosheet FETs with Record-high Ion>2 mA/μm Enabled by
Session: Session T3: 2D Channel Materials
https://www.vlsisymposium.org/wp-content/uploads/2026/05/VLSI26_Program_Finalv2.pdf - Session T4: Oxide Semiconductors
https://www.vlsisymposium.org/wp-content/uploads/2026/05/VLSI26_Program_Finalv2.pdf
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