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2026 08 26 Conference Vlsi Symposium 2026 Program
Official program extract from https://www.vlsisymposium.org/wp-content/uploads/2026/05/VLSI26_Program_Finalv2.pdf. 233 new papers/sessions since last state.
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Summary
Official program extract from https://www.vlsisymposium.org/wp-content/uploads/2026/05/VLSI26_Program_Finalv2.pdf. 233 new papers/sessions since last state. Official page only — titles and authors as listed on the program; no secondary blog coverage.
Program
- T4.1 Different Low-Frequency (1/f) Noise Origins in Atomically Thin ALD In2O3 TFTs Determined by the
Session: Session T4: Oxide Semiconductors
https://www.vlsisymposium.org/wp-content/uploads/2026/05/VLSI26_Program_Finalv2.pdf - T4.2 Hydrogen Overflow as a Novel Negative Vth Shift Mechanism in PBTI Universal to Planar and Vertical
Session: Session T4: Oxide Semiconductors
https://www.vlsisymposium.org/wp-content/uploads/2026/05/VLSI26_Program_Finalv2.pdf - T4.3 First Demonstration of Top-Gated Indium Oxynitride (InON)-FET with Superior Reliability and Contact
Session: Session T4: Oxide Semiconductors
https://www.vlsisymposium.org/wp-content/uploads/2026/05/VLSI26_Program_Finalv2.pdf - T4.4 Breaking Mobility-Vth-RSD Trade-off in Oxide Semiconductor FETs: Novel p-NiO Junction
Session: Session T4: Oxide Semiconductors
https://www.vlsisymposium.org/wp-content/uploads/2026/05/VLSI26_Program_Finalv2.pdf - T4.5 Experimental Study on Carrier Transport in Amorphous and Poly InGaOx FETs – Hall Measurement,
Session: Session T4: Oxide Semiconductors
https://www.vlsisymposium.org/wp-content/uploads/2026/05/VLSI26_Program_Finalv2.pdf - Session TFS1: 3D Memory (Flash/HBM)
https://www.vlsisymposium.org/wp-content/uploads/2026/05/VLSI26_Program_Finalv2.pdf - TFS1.1 3D Flash Memory Technology for the AI Era, Ryota Katsumata1, Seiji Maeda1, Masahiro Inohara1, Hirofumi
Session: Session TFS1: 3D Memory (Flash/HBM)
https://www.vlsisymposium.org/wp-content/uploads/2026/05/VLSI26_Program_Finalv2.pdf - TFS1.2 High Bandwidth Memory 4 (HBM4) Package Development Challenges, Jaesik Lee1, Yeontaek Hwang1,
Session: Session TFS1: 3D Memory (Flash/HBM)
https://www.vlsisymposium.org/wp-content/uploads/2026/05/VLSI26_Program_Finalv2.pdf - TFS1.3 Demonstration of Cell Multi-Bonding (CMB) Technology for Future Vertical NAND over 1kLayer, Jeehoon Han1, Jaeryong Sim1, Seogoo Kang1, Junghoon Jun1, Jihwan Park1, Donghwan Kim1, Changyeon Yu1,
Session: Session TFS1: 3D Memory (Flash/HBM)
https://www.vlsisymposium.org/wp-content/uploads/2026/05/VLSI26_Program_Finalv2.pdf - TFS1.4 Toward Thousands-Layer 3D NAND: Unleashing the Block Size Constraint by Enabling Lateral SubBlock Mode, Wei Cao1, Takayuki Inoue1, Peng Zhang1, Jiacen Guo1, Xiang Yang1, Deepanshu Dutta1
Session: Session TFS1: 3D Memory (Flash/HBM)
https://www.vlsisymposium.org/wp-content/uploads/2026/05/VLSI26_Program_Finalv2.pdf - TFS1.5 A Multi Stacked Cell Array (MSA) Structure with an Up-down Crossed Bit Line Architecture (Ud-CBL) in
Session: Session TFS1: 3D Memory (Flash/HBM)
https://www.vlsisymposium.org/wp-content/uploads/2026/05/VLSI26_Program_Finalv2.pdf - Session P2: Plenary 2
https://www.vlsisymposium.org/wp-content/uploads/2026/05/VLSI26_Program_Finalv2.pdf - P2.1 8:35 AM
Session: Session P2: Plenary 2
https://www.vlsisymposium.org/wp-content/uploads/2026/05/VLSI26_Program_Finalv2.pdf - P2.2 9:15 AM
Session: Session P2: Plenary 2
https://www.vlsisymposium.org/wp-content/uploads/2026/05/VLSI26_Program_Finalv2.pdf - Session C11: Wireless Power Transfer & Energy Harvesting Interfaces
https://www.vlsisymposium.org/wp-content/uploads/2026/05/VLSI26_Program_Finalv2.pdf - C11.1 A 48 V, 25 W, 6.78 MHz Self-Starting Class-D WPT Transmitter with Self-Biasing and Autonomous
Session: Session C11: Wireless Power Transfer & Energy Harvesting Interfaces
https://www.vlsisymposium.org/wp-content/uploads/2026/05/VLSI26_Program_Finalv2.pdf - C11.2 A 6.78MHz Fractional-Resonance Full-Wave Current-Mode Wireless Receiver with Real-Time SARbased Optimum Tracking and Power-Aware Division Control, Jong-Hun Kim1, Seung-Ju Lee1, Seogyong Jeong2,
Session: Session C11: Wireless Power Transfer & Energy Harvesting Interfaces
https://www.vlsisymposium.org/wp-content/uploads/2026/05/VLSI26_Program_Finalv2.pdf - C11.3 A 6.78MHz Fully Integrated Dual-Output Symmetric 1/16-Cycle Regulating Rectifier Achieving 92.57%
Session: Session C11: Wireless Power Transfer & Energy Harvesting Interfaces
https://www.vlsisymposium.org/wp-content/uploads/2026/05/VLSI26_Program_Finalv2.pdf - C11.4 A CMOS Energy Harvesting System Integrating SIDO/DISO Continuously-Scalable- Conversion-Ratio
Session: Session C11: Wireless Power Transfer & Energy Harvesting Interfaces
https://www.vlsisymposium.org/wp-content/uploads/2026/05/VLSI26_Program_Finalv2.pdf - C11.5 A Universal Piezoelectric Energy-Harvesting Interface with Machine Learning-Based Excitation
Session: Session C11: Wireless Power Transfer & Energy Harvesting Interfaces
https://www.vlsisymposium.org/wp-content/uploads/2026/05/VLSI26_Program_Finalv2.pdf - Session C12: True Random Number Generators
https://www.vlsisymposium.org/wp-content/uploads/2026/05/VLSI26_Program_Finalv2.pdf - C12.1 An 80.198um2 Compact TRNG with Bias Mitigation, Proven PVT Tolerance in 4nm, Yunhyeok Choi1, Yong
Session: Session C12: True Random Number Generators
https://www.vlsisymposium.org/wp-content/uploads/2026/05/VLSI26_Program_Finalv2.pdf - C12.2 A 0.33 pJ/b Differential CMOS Thyristor-based TRNG with PVT Tolerance and LSB Min-Entropy
Session: Session C12: True Random Number Generators
https://www.vlsisymposium.org/wp-content/uploads/2026/05/VLSI26_Program_Finalv2.pdf - C12.3 A 5GS/s Staggered Working Point Ensemble TRNG with a Stochastic Model Achieving 4064.5 Mbps
Session: Session C12: True Random Number Generators
https://www.vlsisymposium.org/wp-content/uploads/2026/05/VLSI26_Program_Finalv2.pdf - C12.4 A 0.511 pJ/bit Data-Independent and Post-Processing-Free 6T-SRAM-Based TRNG Exploiting
Session: Session C12: True Random Number Generators
https://www.vlsisymposium.org/wp-content/uploads/2026/05/VLSI26_Program_Finalv2.pdf - Session JFS2: Sensor Devices & Circuits
https://www.vlsisymposium.org/wp-content/uploads/2026/05/VLSI26_Program_Finalv2.pdf - JFS2.1 Flexible Monolithic 3D Integration of RRAM-based CIM, CNT CMOS Circuits and IGZO FET-based
Session: Session JFS2: Sensor Devices & Circuits
https://www.vlsisymposium.org/wp-content/uploads/2026/05/VLSI26_Program_Finalv2.pdf - JFS2.2 Depletion-Mode III-V/Si SISCAP Mach-Zehnder Modulator Breaking the Efficiency-Bandwidth TradeOff for Co-Packaged Optics, Donggil Kang1, Shin Hyung Lee1, Jae-Hoon Han2, Jongmin Kim3, Seok-Geun Ahn4,
Session: Session JFS2: Sensor Devices & Circuits
https://www.vlsisymposium.org/wp-content/uploads/2026/05/VLSI26_Program_Finalv2.pdf - JFS2.3 Back-Illuminated CMOS-SPAD With Full-Surround Anode Structure Achieving Sub-50 ps Timing Jitter
Session: Session JFS2: Sensor Devices & Circuits
https://www.vlsisymposium.org/wp-content/uploads/2026/05/VLSI26_Program_Finalv2.pdf - JFS2.4 A Highly Scalable and Noise-Robust Direct Digital Readout (DDRO) for E-Skin Temperature Sensor
Session: Session JFS2: Sensor Devices & Circuits
https://www.vlsisymposium.org/wp-content/uploads/2026/05/VLSI26_Program_Finalv2.pdf - JFS2.5 A 3D-Conformal Flexible X-ray Detector with 2.06pArms Ultra-Low Noise Readout Circuit Enabling LowDose Computed Tomography Imaging, Zhongqiu Shen1, Kaiwen Zhou1, Shi Chen1, Shen Ye1, Zhiliang Hong1,
Session: Session JFS2: Sensor Devices & Circuits
https://www.vlsisymposium.org/wp-content/uploads/2026/05/VLSI26_Program_Finalv2.pdf - Session T5: Technology Highlights 2
https://www.vlsisymposium.org/wp-content/uploads/2026/05/VLSI26_Program_Finalv2.pdf - T5.1 Vertically Stacked DRAM Technology for Scaling Evolution, Seung Uk Han1, Jin-Woo Han1, Gyuhwan Oh1,
Session: Session T5: Technology Highlights 2
https://www.vlsisymposium.org/wp-content/uploads/2026/05/VLSI26_Program_Finalv2.pdf - T5.2 Demonstration of CFET Inverters on Si (110) with 2X2 RibbonFETs at 45nm Gate Pitch with PowerVia and
Session: Session T5: Technology Highlights 2
https://www.vlsisymposium.org/wp-content/uploads/2026/05/VLSI26_Program_Finalv2.pdf - T5.3 Record 2Pr (>38 μC/cm2 at 0.5 V, >28 μC/cm2 at 0.4 V) of 3D MFM Capacitors Enabled by 3 nm HZO and
Session: Session T5: Technology Highlights 2
https://www.vlsisymposium.org/wp-content/uploads/2026/05/VLSI26_Program_Finalv2.pdf - T5.4 High-Temperature Resilient SiGe Nanosheet PFET RMG Towards Multi-Tiered Sequential
Session: Session T5: Technology Highlights 2
https://www.vlsisymposium.org/wp-content/uploads/2026/05/VLSI26_Program_Finalv2.pdf - T5.5 A 2.1-μm Pixel-Pitch CMOS Image Sensor with 65% MTF/35% QE IR Global Shutter and RGB Rolling
Session: Session T5: Technology Highlights 2
https://www.vlsisymposium.org/wp-content/uploads/2026/05/VLSI26_Program_Finalv2.pdf - Session C13: In-Body Bioelectronic Systems
https://www.vlsisymposium.org/wp-content/uploads/2026/05/VLSI26_Program_Finalv2.pdf - C13.1 A Split-Inference Intracortical Interface IC for Battery-Free mm-Scale Magnetoelectrically Powered
Session: Session C13: In-Body Bioelectronic Systems
https://www.vlsisymposium.org/wp-content/uploads/2026/05/VLSI26_Program_Finalv2.pdf - C13.2 A Wireless Pressure Sensor Implant with MRI-Encoded Data Uplink, Biqi Rebekah Zhao1, Alexander
Session: Session C13: In-Body Bioelectronic Systems
https://www.vlsisymposium.org/wp-content/uploads/2026/05/VLSI26_Program_Finalv2.pdf - C13.3 GMINI: Gut Modulating Neural Interface Chip for Closed-loop Non-invasive Therapies, Adam Gierlach1,
Session: Session C13: In-Body Bioelectronic Systems
https://www.vlsisymposium.org/wp-content/uploads/2026/05/VLSI26_Program_Finalv2.pdf - C13.4 A 50-mm2 Crystal-Free Bidirectional WPDT System with Carrier-Reuse Clocking for Implantable
Session: Session C13: In-Body Bioelectronic Systems
https://www.vlsisymposium.org/wp-content/uploads/2026/05/VLSI26_Program_Finalv2.pdf - Session C14: Adaptive and Agile Radio Architectures
https://www.vlsisymposium.org/wp-content/uploads/2026/05/VLSI26_Program_Finalv2.pdf - C14.1 A Reconfigurable 24-28GHz Time-Division Full-Duplex Transceiver with 59dB Self-Interference
Session: Session C14: Adaptive and Agile Radio Architectures
https://www.vlsisymposium.org/wp-content/uploads/2026/05/VLSI26_Program_Finalv2.pdf - C14.2 A 1.5-to-20.5 GHz Intrinsic-Spurious-Rejection Real-IF Dual-Translation Transceiver Chipset Achieving
Session: Session C14: Adaptive and Agile Radio Architectures
https://www.vlsisymposium.org/wp-content/uploads/2026/05/VLSI26_Program_Finalv2.pdf - C14.3 A 57–71-GHz CMOS Phased-Array Transceiver with Aperture-Tuning Antenna Achieving 47.9–62.2%
Session: Session C14: Adaptive and Agile Radio Architectures
https://www.vlsisymposium.org/wp-content/uploads/2026/05/VLSI26_Program_Finalv2.pdf - C14.4 An 8-Element 200-MHz Bandwidth Oversampling Digital Slepian Beamformer, Zhengqi Xu1,2, Zhiyuan
Session: Session C14: Adaptive and Agile Radio Architectures
https://www.vlsisymposium.org/wp-content/uploads/2026/05/VLSI26_Program_Finalv2.pdf - Session C15: Power Integrity: Regulators, References, and Monitors
https://www.vlsisymposium.org/wp-content/uploads/2026/05/VLSI26_Program_Finalv2.pdf - C15.1 A Robust, Digital-Friendly, Differential and Distributed Supply Monitor Architecture for Automotive
Session: Session C15: Power Integrity: Regulators, References, and Monitors
https://www.vlsisymposium.org/wp-content/uploads/2026/05/VLSI26_Program_Finalv2.pdf - C15.2 A 10-MHz Integrated Voltage Regulator with Cycle-Accurate and Lightweight Predictive Control
Session: Session C15: Power Integrity: Regulators, References, and Monitors
https://www.vlsisymposium.org/wp-content/uploads/2026/05/VLSI26_Program_Finalv2.pdf - C15.3 A Hybrid LDO with Region-Detection and Power-Supply-Rejection-Based Control Achieving High PSR
Session: Session C15: Power Integrity: Regulators, References, and Monitors
https://www.vlsisymposium.org/wp-content/uploads/2026/05/VLSI26_Program_Finalv2.pdf - C15.4 A 0.75V, 1.43%-Inaccuracy 4T MOS-Based Voltage Reference in 251μm² Area, Szu-Lin Liu1, Bei-Shing
Session: Session C15: Power Integrity: Regulators, References, and Monitors
https://www.vlsisymposium.org/wp-content/uploads/2026/05/VLSI26_Program_Finalv2.pdf - Session C16: Low-Power Oscillators and Digital Techniques
https://www.vlsisymposium.org/wp-content/uploads/2026/05/VLSI26_Program_Finalv2.pdf - C16.1 A 5.7–6.8GHz Capacitively-Coupled Series-Assisted Parallel-Resonance VCO Achieving -148.8 dBc/Hz
Session: Session C16: Low-Power Oscillators and Digital Techniques
https://www.vlsisymposium.org/wp-content/uploads/2026/05/VLSI26_Program_Finalv2.pdf - C16.2 A Compact Magnetically Coupled Dual-Mode Class-F-1 VCO Covering 5.8-9.97 GHz with 196.2 dBc/Hz
Session: Session C16: Low-Power Oscillators and Digital Techniques
https://www.vlsisymposium.org/wp-content/uploads/2026/05/VLSI26_Program_Finalv2.pdf - C16.3 A Versatile On-Chip Jitter Measurement Circuit with Dynamic Quantizer-Resolution Adaptation for
Session: Session C16: Low-Power Oscillators and Digital Techniques
https://www.vlsisymposium.org/wp-content/uploads/2026/05/VLSI26_Program_Finalv2.pdf - C16.4 A 20T Low-Power Single-Phase Full-Static Contention-Free Flip-Flop with Inter-Latch Transistor
Session: Session C16: Low-Power Oscillators and Digital Techniques
https://www.vlsisymposium.org/wp-content/uploads/2026/05/VLSI26_Program_Finalv2.pdf - Session T6: BEOL Processes and Devices
https://www.vlsisymposium.org/wp-content/uploads/2026/05/VLSI26_Program_Finalv2.pdf - T6.1 Topological Semimetal MoP as Future Conductors in Back-End-of-Line: Thin Film Deposition, Resistivity
Session: Session T6: BEOL Processes and Devices
https://www.vlsisymposium.org/wp-content/uploads/2026/05/VLSI26_Program_Finalv2.pdf - T6.2 Resistivity scaling of topological CoSi wires to sub-10 nm for post-Cu interconnects, Guy Cohen1, Franco
Session: Session T6: BEOL Processes and Devices
https://www.vlsisymposium.org/wp-content/uploads/2026/05/VLSI26_Program_Finalv2.pdf - T6.3 BEOL-Compatible Oxide Semiconductor Twin-Gate FeFET Achieving a Record-High Memory
Session: Session T6: BEOL Processes and Devices
https://www.vlsisymposium.org/wp-content/uploads/2026/05/VLSI26_Program_Finalv2.pdf - T6.4 Performance Improvement from Subtractive Ruthenium Interconnects with Airgap, Akshit Peer1, Ananya
Session: Session T6: BEOL Processes and Devices
https://www.vlsisymposium.org/wp-content/uploads/2026/05/VLSI26_Program_Finalv2.pdf - Session T7: Gate Stack Processes
https://www.vlsisymposium.org/wp-content/uploads/2026/05/VLSI26_Program_Finalv2.pdf - T7.1 Ultra-scaled high-k gate stacks (CET 0.9 nm) enabled by a low-thermal-budget (500 °C) oxygenpassivated interfacial layer (O-PAS IL), Yukinori Morita1,2, Takamasa Kawanago1,2, Takefumi Kamioka1,2, Yuichiro
Session: Session T7: Gate Stack Processes
https://www.vlsisymposium.org/wp-content/uploads/2026/05/VLSI26_Program_Finalv2.pdf - T7.2 Dipole material-independent carrier mobility in dipole-first nMOS gate stack and introduction of multiVt patterning-tolerant dipole-middle integration for NS/CFET, Hiroaki Arimura1, Leo Lukose1, Jimmy Stiers1,
Session: Session T7: Gate Stack Processes
https://www.vlsisymposium.org/wp-content/uploads/2026/05/VLSI26_Program_Finalv2.pdf - T7.3 Mitigating intrinsic fixed-charge-induced Vfb fluctuation using a “neutral TiO2 dipole” layer, Takefumi
Session: Session T7: Gate Stack Processes
https://www.vlsisymposium.org/wp-content/uploads/2026/05/VLSI26_Program_Finalv2.pdf - T7.4 Effective Dipole Strength Modulation using Imprinted Gadolinium Dipole (IGD) Layer to Achieve Fine
Session: Session T7: Gate Stack Processes
https://www.vlsisymposium.org/wp-content/uploads/2026/05/VLSI26_Program_Finalv2.pdf - Session C17: High Speed ADCs
https://www.vlsisymposium.org/wp-content/uploads/2026/05/VLSI26_Program_Finalv2.pdf - C17.1 A 12-bit 4-GS/s ADC with PLL-based Sub-ranging RO-TDC, Yimeng Wang1,2, Xinyang Di1,2, Jingxiang
Session: Session C17: High Speed ADCs
https://www.vlsisymposium.org/wp-content/uploads/2026/05/VLSI26_Program_Finalv2.pdf - C17.2 A 3.2GS/s 2nd-order Noise-Shaping-Pipelined ADC with 400MHz-BW 69dB-SNDR Featuring
Session: Session C17: High Speed ADCs
https://www.vlsisymposium.org/wp-content/uploads/2026/05/VLSI26_Program_Finalv2.pdf - C17.3 An 8bit 4.8GS/s 10.9fJ/conv.-step TI-SAR ADC with 4bit/3cycle Ping-Pong Architecture and Data-Driven
Session: Session C17: High Speed ADCs
https://www.vlsisymposium.org/wp-content/uploads/2026/05/VLSI26_Program_Finalv2.pdf - C17.4 A 14b 500MS/s Pipelined-SAR ADC with Loop-Unrolled Correlated Level Shifting and Rapid Sequential
Session: Session C17: High Speed ADCs
https://www.vlsisymposium.org/wp-content/uploads/2026/05/VLSI26_Program_Finalv2.pdf - C17.5 A 19.4mW 2.5GS/s Pipelined-SAR ADC Achieving 60.8dB SNDR Employing a Dual-Zero-Compensation
Session: Session C17: High Speed ADCs
https://www.vlsisymposium.org/wp-content/uploads/2026/05/VLSI26_Program_Finalv2.pdf - Session C18: Display Interfaces and Data Conversion Circuits
https://www.vlsisymposium.org/wp-content/uploads/2026/05/VLSI26_Program_Finalv2.pdf - C18.1 A 3200×2880, 120Hz OLED Display Driver IC with Miller-Charge Cancellation (MCC) Achieving a
Session: Session C18: Display Interfaces and Data Conversion Circuits
https://www.vlsisymposium.org/wp-content/uploads/2026/05/VLSI26_Program_Finalv2.pdf - C18.2 A 95.0 dB Dynamic Range Zero-Bias PV Light-to-Digital Converter for Seawater Monitoring with Single
Session: Session C18: Display Interfaces and Data Conversion Circuits
https://www.vlsisymposium.org/wp-content/uploads/2026/05/VLSI26_Program_Finalv2.pdf - C18.3 A 28nm 2GS/s Remote-Sensing On-Chip Oscilloscope Using Charge-Redistributing Voltage Transfer
Session: Session C18: Display Interfaces and Data Conversion Circuits
https://www.vlsisymposium.org/wp-content/uploads/2026/05/VLSI26_Program_Finalv2.pdf - C18.4 An 11b Source-Driver IC with Resistor-Resistor-Embedded (RRE) DAC and Multi-Step Offset
Session: Session C18: Display Interfaces and Data Conversion Circuits
https://www.vlsisymposium.org/wp-content/uploads/2026/05/VLSI26_Program_Finalv2.pdf - C18.5 A 10-Bit Source-Driver IC with Mismatch-Resilient Cross-Point DAC Achieving 1223μm2/Channel and
Session: Session C18: Display Interfaces and Data Conversion Circuits
https://www.vlsisymposium.org/wp-content/uploads/2026/05/VLSI26_Program_Finalv2.pdf - Session C19: Bio-Sensing and Molecular Interfaces
https://www.vlsisymposium.org/wp-content/uploads/2026/05/VLSI26_Program_Finalv2.pdf
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