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2026 08 27 Conference Vlsi Symposium 2026 Program
Official program extract from https://www.vlsisymposium.org/wp-content/uploads/2026/05/VLSI26_Program_Finalv2.pdf. 153 new papers/sessions since last state.
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Summary
Official program extract from https://www.vlsisymposium.org/wp-content/uploads/2026/05/VLSI26_Program_Finalv2.pdf. 153 new papers/sessions since last state. Official page only — titles and authors as listed on the program; no secondary blog coverage.
Program
- C19.1 300-Channel Photometry Neural Probe with In-Pixel Adaptive-Noise ΔΣ Modulators Achieving 16.8
Session: Session C19: Bio-Sensing and Molecular Interfaces
https://www.vlsisymposium.org/wp-content/uploads/2026/05/VLSI26_Program_Finalv2.pdf - C19.2 A Scalable, Unified Current-Mode ΔΣ Redox/pH Readout with Shared Potentiostat and Flicker-Noise
Session: Session C19: Bio-Sensing and Molecular Interfaces
https://www.vlsisymposium.org/wp-content/uploads/2026/05/VLSI26_Program_Finalv2.pdf - C19.3 An 83.5dB DR, 74pARMS Neurotransmitter Sensor Interface with Drift Correction, Wangbo Chen1, Jose R
Session: Session C19: Bio-Sensing and Molecular Interfaces
https://www.vlsisymposium.org/wp-content/uploads/2026/05/VLSI26_Program_Finalv2.pdf - C19.4 A 16-channel 97pArms 1MHz Bandwidth IC for Solid State Nanopore Sequencing, Qiuyang Lin1, Wim
Session: Session C19: Bio-Sensing and Molecular Interfaces
https://www.vlsisymposium.org/wp-content/uploads/2026/05/VLSI26_Program_Finalv2.pdf - C19.5 Filter-free Time-gated Fluorescence CMOS Biochip with Fast Thermal Cycling for PoC DNA
Session: Session C19: Bio-Sensing and Molecular Interfaces
https://www.vlsisymposium.org/wp-content/uploads/2026/05/VLSI26_Program_Finalv2.pdf - Session T8: DRAM
https://www.vlsisymposium.org/wp-content/uploads/2026/05/VLSI26_Program_Finalv2.pdf - T8.1 3D Orthogonal Die Stacking Technology for DRAM-on-GPU Integration Using Contactless Die-to-Die
Session: Session T8: DRAM
https://www.vlsisymposium.org/wp-content/uploads/2026/05/VLSI26_Program_Finalv2.pdf - T8.2 Highly stackable 3D DRAM of Dual-gate IGZO 2T0C with Record 3 bits/cell and 400s Data Retention, Fuxi
Session: Session T8: DRAM
https://www.vlsisymposium.org/wp-content/uploads/2026/05/VLSI26_Program_Finalv2.pdf - T8.3 A High-Performance Heterogeneous 2T0C DRAM with PSLC-Si/IGZO Complementary Gain Cell for
Session: Session T8: DRAM
https://www.vlsisymposium.org/wp-content/uploads/2026/05/VLSI26_Program_Finalv2.pdf - T8.4 Vertical-Die (V-die) 3.5D Integration for Cool Ultrahigh-Bandwidth Memory Systems, Heesoo Yang1,
Session: Session T8: DRAM
https://www.vlsisymposium.org/wp-content/uploads/2026/05/VLSI26_Program_Finalv2.pdf - T8.5 Electrical Characteristics of the 4F2 Vertical Gate (VG) DRAM integrated with Bit-Line Shielding (BLS) and
Session: Session T8: DRAM
https://www.vlsisymposium.org/wp-content/uploads/2026/05/VLSI26_Program_Finalv2.pdf - Session T9: Ferroelectric Materials for Memory
https://www.vlsisymposium.org/wp-content/uploads/2026/05/VLSI26_Program_Finalv2.pdf - T9.1 Origin and Modeling of the Access-Rate-Dependent Degradation and Dual-Interface Optimization in
Session: Session T9: Ferroelectric Materials for Memory
https://www.vlsisymposium.org/wp-content/uploads/2026/05/VLSI26_Program_Finalv2.pdf - T9.2 Improved disturb-free memory window, retention and endurance in low-voltage 3D-FeFETs by
Session: Session T9: Ferroelectric Materials for Memory
https://www.vlsisymposium.org/wp-content/uploads/2026/05/VLSI26_Program_Finalv2.pdf - T9.3 First Demonstration of Highly-Scaled Trench-Structured Ferroelectric Capacitive Memory with RecordHigh Capacitive Memory Window and Integrated ITO Sensing FET, Jingguang Lu1,2, Zuopu Zhou3, Leming Jiao1,
Session: Session T9: Ferroelectric Materials for Memory
https://www.vlsisymposium.org/wp-content/uploads/2026/05/VLSI26_Program_Finalv2.pdf - T9.4 Engineering 3D HZO ferroelectric capacitors to scale down 22nm embedded FeRAM, Carine Jahan1,
Session: Session T9: Ferroelectric Materials for Memory
https://www.vlsisymposium.org/wp-content/uploads/2026/05/VLSI26_Program_Finalv2.pdf - T9.5 Record-Thin (~2 nm) Wakeup-Free HZO Ferroelectric MFM via Atomic Layer Etching (ALE): Grain Size
Session: Session T9: Ferroelectric Materials for Memory
https://www.vlsisymposium.org/wp-content/uploads/2026/05/VLSI26_Program_Finalv2.pdf - Session TFS2: Advanced 3D Logic
https://www.vlsisymposium.org/wp-content/uploads/2026/05/VLSI26_Program_Finalv2.pdf - TFS2.1 CFET Demonstration for Future Logic and SRAM Technology, Szuya Sandy Liao1, Lu Yang1, Wei-Xiang
Session: Session TFS2: Advanced 3D Logic
https://www.vlsisymposium.org/wp-content/uploads/2026/05/VLSI26_Program_Finalv2.pdf - TFS2.2 Backside Power: Enabling Energy Efficient Performance on Advanced Node Designs, Eric Karl1, Shishir
Session: Session TFS2: Advanced 3D Logic
https://www.vlsisymposium.org/wp-content/uploads/2026/05/VLSI26_Program_Finalv2.pdf - TFS2.3 A Product-Oriented 3rd-Generation 2nm GAA Platform Technology with Enhanced Speed and Power
Session: Session TFS2: Advanced 3D Logic
https://www.vlsisymposium.org/wp-content/uploads/2026/05/VLSI26_Program_Finalv2.pdf - TFS2.4 Backside Split-VDD Write-Assist Driven SRAM Macro Scaling in Nanosheet-Era, Ankit Singh1, Dawit
Session: Session TFS2: Advanced 3D Logic
https://www.vlsisymposium.org/wp-content/uploads/2026/05/VLSI26_Program_Finalv2.pdf - TFS2.5 Area and Performance of Staggered-Channel Nanostack SRAM Bitcells, Chen Zhang1, Carl Radens1,
Session: Session TFS2: Advanced 3D Logic
https://www.vlsisymposium.org/wp-content/uploads/2026/05/VLSI26_Program_Finalv2.pdf - Session Banquet: Hawaiian Luau and Banquet
https://www.vlsisymposium.org/wp-content/uploads/2026/05/VLSI26_Program_Finalv2.pdf - Session C20: Next-Generation Optical Transceivers
https://www.vlsisymposium.org/wp-content/uploads/2026/05/VLSI26_Program_Finalv2.pdf - C20.1 An 800 Gbps/Fiber Silicon Photonic Microring-Based DWDM Transceiver in an Open-Cavity
Session: Session C20: Next-Generation Optical Transceivers
https://www.vlsisymposium.org/wp-content/uploads/2026/05/VLSI26_Program_Finalv2.pdf - C20.2 A 32Gb/s Optical Receiver utilizing a Differential TIA with -17.3dBm Sensitivity in a 3D-stacked Silicon
Session: Session C20: Next-Generation Optical Transceivers
https://www.vlsisymposium.org/wp-content/uploads/2026/05/VLSI26_Program_Finalv2.pdf - C20.3 A 0.69-pJ/b 4x80-Gb/s MRM-Based Coherent Optical Transmitter with Time-Multiplexed Thermal
Session: Session C20: Next-Generation Optical Transceivers
https://www.vlsisymposium.org/wp-content/uploads/2026/05/VLSI26_Program_Finalv2.pdf - C20.4 A 0.416-pJ/b, 32-Gb/s 3D-Stacked Optical NRZ Receiver with -18.5-dBm OMA Sensitivity Using SelfTimed Decision Feedback Equalization, Li Xu1, Sanquan Song1, Nikola Nedovic1, Georgios Kalogerakis1, Nandish
Session: Session C20: Next-Generation Optical Transceivers
https://www.vlsisymposium.org/wp-content/uploads/2026/05/VLSI26_Program_Finalv2.pdf - Session C21: SoCs for Reasoning and Robotics
https://www.vlsisymposium.org/wp-content/uploads/2026/05/VLSI26_Program_Finalv2.pdf - C21.1 TinyNPU: A 3nm 0.06-134.36 μJ/token DCIM-Based Ultra Low Power NPU for Always-On Reasoning on
Session: Session C21: SoCs for Reasoning and Robotics
https://www.vlsisymposium.org/wp-content/uploads/2026/05/VLSI26_Program_Finalv2.pdf - C21.2 μAgent: A 7nm 404.3mJ/Action Edge SoC for Agentic AI Reasoning with Adaptive Block-wise MixedFormat 4-bit Quantization and Decoupled Access-Execute, Wonsuk Jang1, Christian Kubicka1, Allen Pan1,
Session: Session C21: SoCs for Reasoning and Robotics
https://www.vlsisymposium.org/wp-content/uploads/2026/05/VLSI26_Program_Finalv2.pdf - C21.3 Sirius: A Dual-Chiplet System for Multimodal Embodied AI with Heterogeneous RVV Cores, Dense and
Session: Session C21: SoCs for Reasoning and Robotics
https://www.vlsisymposium.org/wp-content/uploads/2026/05/VLSI26_Program_Finalv2.pdf - C21.4 A Scalable Vision-Language-Action Edge Processor with Token Filtering and Hybrid Processing-NearMemory for 6.7-ms Perception-to-Action Latency in Robot Control, Jin Wang1, Zhengke Yang1, Yulong Chen1,
Session: Session C21: SoCs for Reasoning and Robotics
https://www.vlsisymposium.org/wp-content/uploads/2026/05/VLSI26_Program_Finalv2.pdf - Session C22: Fast and High-PSR On-Chip LDO Regulation
https://www.vlsisymposium.org/wp-content/uploads/2026/05/VLSI26_Program_Finalv2.pdf - C22.1 A 1-to-1050-mA DLDO with Rising-Edge Computational Control and Load-Dependent Feedback
Session: Session C22: Fast and High-PSR On-Chip LDO Regulation
https://www.vlsisymposium.org/wp-content/uploads/2026/05/VLSI26_Program_Finalv2.pdf - C22.2 A Scalable Distributed Digital LDO Achieving Fast and Accurate Current Balancing, Sang-Yun Nam1,
Session: Session C22: Fast and High-PSR On-Chip LDO Regulation
https://www.vlsisymposium.org/wp-content/uploads/2026/05/VLSI26_Program_Finalv2.pdf - C22.3 A Fully Integrated, GBW-Enhanced Tri-Loop, Maximum Ripple Rejection Tracking Analog LDO
Session: Session C22: Fast and High-PSR On-Chip LDO Regulation
https://www.vlsisymposium.org/wp-content/uploads/2026/05/VLSI26_Program_Finalv2.pdf - C22.4 A Floating-Inverter Integrator LDO Achieving Near-Zero Line Regulation via Parasitic-Synthesized
Session: Session C22: Fast and High-PSR On-Chip LDO Regulation
https://www.vlsisymposium.org/wp-content/uploads/2026/05/VLSI26_Program_Finalv2.pdf - Session JFS3: DTCO
https://www.vlsisymposium.org/wp-content/uploads/2026/05/VLSI26_Program_Finalv2.pdf - JFS3.1 5T+1 CFET SRAM with Dual-Bitline-per-Cell-Height Enabling Differential Readout and 12.5% Area
Session: Session JFS3: DTCO
https://www.vlsisymposium.org/wp-content/uploads/2026/05/VLSI26_Program_Finalv2.pdf - JFS3.2 Scaling High Density Designs Towards Angstrom Nodes: BEOL Routability, Pin Accessibility
Session: Session JFS3: DTCO
https://www.vlsisymposium.org/wp-content/uploads/2026/05/VLSI26_Program_Finalv2.pdf - JFS3.3 An Innovative DTCO for 2 nm GAA Technology with Hyper-cells in an Extremely High-Density Library
Session: Session JFS3: DTCO
https://www.vlsisymposium.org/wp-content/uploads/2026/05/VLSI26_Program_Finalv2.pdf - JFS3.4 ESD and Circuit Performance DTCO in 2nm CMOS Nanosheet Technology, Tao-Yi Hung1, Li-Wei Chu1,
Session: Session JFS3: DTCO
https://www.vlsisymposium.org/wp-content/uploads/2026/05/VLSI26_Program_Finalv2.pdf - Session T10: Process Technology for CMOS Scaling
https://www.vlsisymposium.org/wp-content/uploads/2026/05/VLSI26_Program_Finalv2.pdf - T10.1 First Demonstration of Metal Interconnect At-Resolution Stitching with 0.55NA EUV Lithography for
Session: Session T10: Process Technology for CMOS Scaling
https://www.vlsisymposium.org/wp-content/uploads/2026/05/VLSI26_Program_Finalv2.pdf - T10.2 First Demonstration of a Functional Gate-All-Around Nanosheet CMOS Circuit Using Single Exposure
Session: Session T10: Process Technology for CMOS Scaling
https://www.vlsisymposium.org/wp-content/uploads/2026/05/VLSI26_Program_Finalv2.pdf - T10.3 High Yield Sub 20 nm Ru Direct Metal Etch Enabled by Single-Exposure 0.55NA EUV and dry MOR
Session: Session T10: Process Technology for CMOS Scaling
https://www.vlsisymposium.org/wp-content/uploads/2026/05/VLSI26_Program_Finalv2.pdf - T10.4 Direct Synthesis of Multi-stacked Channels and Doped Source/Drains for TMD CFETs, Shinichi Tanabe1,
Session: Session T10: Process Technology for CMOS Scaling
https://www.vlsisymposium.org/wp-content/uploads/2026/05/VLSI26_Program_Finalv2.pdf - Session T11: FeRAM Array and Module
https://www.vlsisymposium.org/wp-content/uploads/2026/05/VLSI26_Program_Finalv2.pdf - T11.1 3D Vertical FeFET Array with Record Endurance (>1012), Fast Writing (±2V, 20 ns), Disturb Immunity, and
Session: Session T11: FeRAM Array and Module
https://www.vlsisymposium.org/wp-content/uploads/2026/05/VLSI26_Program_Finalv2.pdf - T11.2 First Demonstration of Bit-Cost Scalable and BEOL-Compatible Monolithic 4-Tier FeRAM Operating at
Session: Session T11: FeRAM Array and Module
https://www.vlsisymposium.org/wp-content/uploads/2026/05/VLSI26_Program_Finalv2.pdf - T11.3 High-Performance Normally-off IGZO FeFETs with Thermally Stable Ru S/D for Power-Efficient Memory
Session: Session T11: FeRAM Array and Module
https://www.vlsisymposium.org/wp-content/uploads/2026/05/VLSI26_Program_Finalv2.pdf - T11.4 Interfacial engineering of scaled HZO in 3D-trench BEOL-compatible FeCAPs for high endurance
Session: Session T11: FeRAM Array and Module
https://www.vlsisymposium.org/wp-content/uploads/2026/05/VLSI26_Program_Finalv2.pdf - Session C23: ASICs for Emerging Workloads
https://www.vlsisymposium.org/wp-content/uploads/2026/05/VLSI26_Program_Finalv2.pdf - C23.1 A 90.6 pJ / pixel 1280x800 65 fps cm-Scale Fully Integrated Video Encoder System Utilizing a 2x2
Session: Session C23: ASICs for Emerging Workloads
https://www.vlsisymposium.org/wp-content/uploads/2026/05/VLSI26_Program_Finalv2.pdf - C23.2 Specter: 376 fps 2.67 nJ/pixel 4DGS Processor for Spatiotemporal Reconstruction with ContributionOrdered Rendering and Deformation-Aware Modeling, Jae-Young Kim1, Teokkyu Suh1, Junsoo Lim1, Minjun Park1,
Session: Session C23: ASICs for Emerging Workloads
https://www.vlsisymposium.org/wp-content/uploads/2026/05/VLSI26_Program_Finalv2.pdf - C23.3 HCNP: A 70.2 TOPS/W Hybrid CIM-NPU Processor with In-Streaming Processing for Energy Efficient
Session: Session C23: ASICs for Emerging Workloads
https://www.vlsisymposium.org/wp-content/uploads/2026/05/VLSI26_Program_Finalv2.pdf - C23.4 A 248.5 GFLOPS/mm2, 1.67 TFLOPS/W Streaming Processor with Hardware-Level Scheduling for
Session: Session C23: ASICs for Emerging Workloads
https://www.vlsisymposium.org/wp-content/uploads/2026/05/VLSI26_Program_Finalv2.pdf - Session C24: Circuits for Bio-Signal Acquisition and Neural Interfaces
https://www.vlsisymposium.org/wp-content/uploads/2026/05/VLSI26_Program_Finalv2.pdf - C24.1 A Sub-µW VCO-Based Direct Digitization Front-End with an Auto-Ranging Technique Achieving 1.8 NEF
Session: Session C24: Circuits for Bio-Signal Acquisition and Neural Interfaces
https://www.vlsisymposium.org/wp-content/uploads/2026/05/VLSI26_Program_Finalv2.pdf - C24.2 A 256-Channel, 32-Interconnect, 1.25-NEF, In vitro and In vivo Neural Interface with Auto-Calibrated
Session: Session C24: Circuits for Bio-Signal Acquisition and Neural Interfaces
https://www.vlsisymposium.org/wp-content/uploads/2026/05/VLSI26_Program_Finalv2.pdf - C24.3 A 1V Time-Division-Multiplexed 4-Channel 3rd-Order NS-SAR ADC with 178.8dB FoMDR and 5.8GΩ Input
Session: Session C24: Circuits for Bio-Signal Acquisition and Neural Interfaces
https://www.vlsisymposium.org/wp-content/uploads/2026/05/VLSI26_Program_Finalv2.pdf - C24.4 A 4.32uW/Ch 256-Channel Neural Probe Integrating in-situ ADC and Stimulation for Closed-Loop
Session: Session C24: Circuits for Bio-Signal Acquisition and Neural Interfaces
https://www.vlsisymposium.org/wp-content/uploads/2026/05/VLSI26_Program_Finalv2.pdf - C24.5 A dynamic supply temporal interference stimulation ASIC achieving 70% peak power saving and 21V
Session: Session C24: Circuits for Bio-Signal Acquisition and Neural Interfaces
https://www.vlsisymposium.org/wp-content/uploads/2026/05/VLSI26_Program_Finalv2.pdf - Session JFS4: More-than-Moore Designs & Robotics
https://www.vlsisymposium.org/wp-content/uploads/2026/05/VLSI26_Program_Finalv2.pdf - JFS4.1 Architecture Partitioning and Optimization in the Era of Chiplet Computing, Vamsi Krishna Alla1, Alan
Session: Session JFS4: More-than-Moore Designs & Robotics
https://www.vlsisymposium.org/wp-content/uploads/2026/05/VLSI26_Program_Finalv2.pdf - JFS4.2 3DIC Design Methodology for High-Performance Computing, Chih-Wei Jim Chang1, Zhe-Wei Jiang1, KingHo Tam1,1, Yun-Han Lee1, Lee-Chung Lu1
Session: Session JFS4: More-than-Moore Designs & Robotics
https://www.vlsisymposium.org/wp-content/uploads/2026/05/VLSI26_Program_Finalv2.pdf - JFS4.3 Integrated Imaging Solutions for Robotic Navigation and Manipulation: Visual-Inertial SLAM and
Session: Session JFS4: More-than-Moore Designs & Robotics
https://www.vlsisymposium.org/wp-content/uploads/2026/05/VLSI26_Program_Finalv2.pdf - JFS4.4 Enabling the Robotic Revolution: Bridging Performance Gap between Present and Future, Qijing
Session: Session JFS4: More-than-Moore Designs & Robotics
https://www.vlsisymposium.org/wp-content/uploads/2026/05/VLSI26_Program_Finalv2.pdf - JFS4.5 Device-to-Architecture Co-design of Monolithic 3D FPGA using 2D transistor, Hyeong-Seok Jang1,
Session: Session JFS4: More-than-Moore Designs & Robotics
https://www.vlsisymposium.org/wp-content/uploads/2026/05/VLSI26_Program_Finalv2.pdf - Session T12: Memory (NAND/NOR/DRAM)
https://www.vlsisymposium.org/wp-content/uploads/2026/05/VLSI26_Program_Finalv2.pdf - T12.1 Deposition Process-Based Charge Trap Layer Segmentation for 3D Flash Memory Achieving Improved
Session: Session T12: Memory (NAND/NOR/DRAM)
https://www.vlsisymposium.org/wp-content/uploads/2026/05/VLSI26_Program_Finalv2.pdf - T12.2 Innovative performance of 6th generation 11nm DRAM cell transistor for HBM4 application, Shinwoo
Session: Session T12: Memory (NAND/NOR/DRAM)
https://www.vlsisymposium.org/wp-content/uploads/2026/05/VLSI26_Program_Finalv2.pdf - T12.3 Uniform and Direction-Controllable Metal-Induced Lateral Crystallization for 3D NAND Flash Memory
Session: Session T12: Memory (NAND/NOR/DRAM)
https://www.vlsisymposium.org/wp-content/uploads/2026/05/VLSI26_Program_Finalv2.pdf - T12.4 A 4Gb 32-Layer 3D NOR Flash Test Chip with Innovative Design Methods Enabling Sub-100ns LowLatency Read and Robust Retention, Hang-Ting Lue1, Teng-Hao Yeh1, Chih-Chang Hsieh1, Tzu-Hsuan Hsu1,
Session: Session T12: Memory (NAND/NOR/DRAM)
https://www.vlsisymposium.org/wp-content/uploads/2026/05/VLSI26_Program_Finalv2.pdf - Session T13: Device Physics and Reliability
https://www.vlsisymposium.org/wp-content/uploads/2026/05/VLSI26_Program_Finalv2.pdf - T13.1 Workload-Derived AC Bias Temperature Instability and Mechanism Contributions in BEOL Oxide
Session: Session T13: Device Physics and Reliability
https://www.vlsisymposium.org/wp-content/uploads/2026/05/VLSI26_Program_Finalv2.pdf - T13.2 Elucidating the Role of Channel Materials and Interlayers in Ferroelectric NAND, Jung-Kyun Kim1, Sijung
Session: Session T13: Device Physics and Reliability
https://www.vlsisymposium.org/wp-content/uploads/2026/05/VLSI26_Program_Finalv2.pdf - T13.3 New Insights into Multi-Level Cell Behavior in FeFET: Localization Effect Aware Write-Verify
Session: Session T13: Device Physics and Reliability
https://www.vlsisymposium.org/wp-content/uploads/2026/05/VLSI26_Program_Finalv2.pdf
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