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2026 08 28 Conference Vlsi Symposium 2026 Program
Official program extract from https://www.vlsisymposium.org/wp-content/uploads/2026/05/VLSI26_Program_Finalv2.pdf. 73 new papers/sessions since last state.
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Summary
Official program extract from https://www.vlsisymposium.org/wp-content/uploads/2026/05/VLSI26_Program_Finalv2.pdf. 73 new papers/sessions since last state. Official page only — titles and authors as listed on the program; no secondary blog coverage.
Program
- T13.4 First Demonstration of CVD Monolayer WSe2 PFETs with Ultra-Short Channel Length of 16 nm:
Session: Session T13: Device Physics and Reliability
https://www.vlsisymposium.org/wp-content/uploads/2026/05/VLSI26_Program_Finalv2.pdf - T13.5 The Thermal Paradox of Oxygen Vacancies: Screening vs. Depolarization Setting the Retention in WDoped Indium Oxide FEFETs, Sharadindu Gopal Kirtania1, Hyeonwoo Park1, Emmanuel Quezada1, Chengyang
Session: Session T13: Device Physics and Reliability
https://www.vlsisymposium.org/wp-content/uploads/2026/05/VLSI26_Program_Finalv2.pdf - Session T14: Emerging NVM: RRAM, MRAM, PCM
https://www.vlsisymposium.org/wp-content/uploads/2026/05/VLSI26_Program_Finalv2.pdf - T14.1 Decoupling Dual Degradation Pathways in OTS Endurance for High-Reliability Selector-Only
Session: Session T14: Emerging NVM: RRAM, MRAM, PCM
https://www.vlsisymposium.org/wp-content/uploads/2026/05/VLSI26_Program_Finalv2.pdf - T14.2 4nm FinFET CMOS Logic Embedded 1T Contact RRAM, Wei-Hwa Lin1, Yen-Yu Liu1, Yue-Der Chih2, Yih
Session: Session T14: Emerging NVM: RRAM, MRAM, PCM
https://www.vlsisymposium.org/wp-content/uploads/2026/05/VLSI26_Program_Finalv2.pdf - T14.3 Scalable and stackable 2S1M SOT-MRAM memory cell enabled by two-terminal write and read SNGCT
Session: Session T14: Emerging NVM: RRAM, MRAM, PCM
https://www.vlsisymposium.org/wp-content/uploads/2026/05/VLSI26_Program_Finalv2.pdf - T14.4 Ultra-Low Drift (4 mV/dec.) and Excellent Write Endurance (> 3×1010) in Heterostructure Te-Based
Session: Session T14: Emerging NVM: RRAM, MRAM, PCM
https://www.vlsisymposium.org/wp-content/uploads/2026/05/VLSI26_Program_Finalv2.pdf - T14.5 Automotive-Grade 5 nm Embedded MRAM with Robust Read Margin from -40℃ to 150℃ via CoOptimized MTJ and Integration, Hyunsung Jung1, Myoungsu Son1, Wanjin Chung1, Jaechul Shim1, Youngkeol Kim1,
Session: Session T14: Emerging NVM: RRAM, MRAM, PCM
https://www.vlsisymposium.org/wp-content/uploads/2026/05/VLSI26_Program_Finalv2.pdf - Session C25: Energy Efficient Wireline Transceivers and Clocking Circuits
https://www.vlsisymposium.org/wp-content/uploads/2026/05/VLSI26_Program_Finalv2.pdf - C25.1 A 2.05pJ/bit, 212.5Gbps DSP based Transceiver with 55dB Reach in 3nm FinFET, M. Gambhir1, A.
Session: Session C25: Energy Efficient Wireline Transceivers and Clocking Circuits
https://www.vlsisymposium.org/wp-content/uploads/2026/05/VLSI26_Program_Finalv2.pdf - C25.2 A 0.06pJ/b Current-Conveyor-based Current-Domain Transceiver with DC-Balanced MultiTransmission-Line PAM Symbol Encoding, Seunghee Han1, Seokman Kim2, Sanghyun Han2, Yeonghwan Kim2,
Session: Session C25: Energy Efficient Wireline Transceivers and Clocking Circuits
https://www.vlsisymposium.org/wp-content/uploads/2026/05/VLSI26_Program_Finalv2.pdf - C25.3 A 16.8–33.6Gb/s, 0.93pJ/b Direct-Frequency-Tracking Digital CDR with an SSC Profile Replicator for
Session: Session C25: Energy Efficient Wireline Transceivers and Clocking Circuits
https://www.vlsisymposium.org/wp-content/uploads/2026/05/VLSI26_Program_Finalv2.pdf - C25.4 A 1.39pJ/bit 224Gb/s PAM-4 Long-Reach SerDes Receiver in 3nm FinFET, Euhan Chong1, Jacob Pike1, Tae
Session: Session C25: Energy Efficient Wireline Transceivers and Clocking Circuits
https://www.vlsisymposium.org/wp-content/uploads/2026/05/VLSI26_Program_Finalv2.pdf - Session C26: UWB, IoT, and RF Enablers
https://www.vlsisymposium.org/wp-content/uploads/2026/05/VLSI26_Program_Finalv2.pdf - C26.1 A 3.25-Gb/s 0.74-pJ/bit IR-UWB Transmitter using Edge-Reference Differential Phase Shift Keying (ERDPSK), Donggun Lee1, Kyoungseok Song1, Sangho Rhee1, Tae Wook Kim1
Session: Session C26: UWB, IoT, and RF Enablers
https://www.vlsisymposium.org/wp-content/uploads/2026/05/VLSI26_Program_Finalv2.pdf - C26.2 A Cross-Band Wi-Fi/BLE Passive Tag Demonstrating Battery-Free Standard-Mask Communication with
Session: Session C26: UWB, IoT, and RF Enablers
https://www.vlsisymposium.org/wp-content/uploads/2026/05/VLSI26_Program_Finalv2.pdf - C26.3 A Switched Inductor-Capacitor Power Amplifier Supporting 100MHz 256-QAM, Yuncheng Zhang1, Duo
Session: Session C26: UWB, IoT, and RF Enablers
https://www.vlsisymposium.org/wp-content/uploads/2026/05/VLSI26_Program_Finalv2.pdf - C26.4 An IEEE 802.15.4z-Compliant IR-UWB System-on-Chip with 27 dB Self-Interference Cancellation and
Session: Session C26: UWB, IoT, and RF Enablers
https://www.vlsisymposium.org/wp-content/uploads/2026/05/VLSI26_Program_Finalv2.pdf - Session C27: Next-Generation Wireless Baseband Processors
https://www.vlsisymposium.org/wp-content/uploads/2026/05/VLSI26_Program_Finalv2.pdf - C27.1 A 17.6Gb/s, 39.1pJ/b Tiled Beamspace Training and Detection Processor for mmWave Massive
Session: Session C27: Next-Generation Wireless Baseband Processors
https://www.vlsisymposium.org/wp-content/uploads/2026/05/VLSI26_Program_Finalv2.pdf - C27.2 A 39pJ/b 7.3Gbps 1.3mm2 Multi-Subcarrier Massive MU-MIMO-OFDM Detector Exploiting Beamspace
Session: Session C27: Next-Generation Wireless Baseband Processors
https://www.vlsisymposium.org/wp-content/uploads/2026/05/VLSI26_Program_Finalv2.pdf - C27.3 A 5.69mm2 6.22Gbps User-Correlation-Based Hybrid Detector for 1024x64 Massive MIMO
Session: Session C27: Next-Generation Wireless Baseband Processors
https://www.vlsisymposium.org/wp-content/uploads/2026/05/VLSI26_Program_Finalv2.pdf - C27.4 A 2.35mm2 118.3Gbps 5.14pJ/bit Dual-Mode LDPC Decoder for 5G/6G, Yuqing Ren1, Yuqi Wang1, Leyu
Session: Session C27: Next-Generation Wireless Baseband Processors
https://www.vlsisymposium.org/wp-content/uploads/2026/05/VLSI26_Program_Finalv2.pdf - Session JFS5: HPC Connectivity
https://www.vlsisymposium.org/wp-content/uploads/2026/05/VLSI26_Program_Finalv2.pdf - JFS5.1 Membrane III-V Photonic Devices on Silicon Photonics Platform for Short-Distance Optical
Session: Session JFS5: HPC Connectivity
https://www.vlsisymposium.org/wp-content/uploads/2026/05/VLSI26_Program_Finalv2.pdf - JFS5.2 A 3-nm FinFET CMOS PAM-4 Retimer for 800-Gb/s and 1.6-Tb/s Optical Modules, Andy Fan, Amrutha
Session: Session JFS5: HPC Connectivity
https://www.vlsisymposium.org/wp-content/uploads/2026/05/VLSI26_Program_Finalv2.pdf - JFS5.3 A Monolithic Optical IQ Coherent Receiver in Unmodified Bulk CMOS, Samir Nooshabadi1, Debjit
Session: Session JFS5: HPC Connectivity
https://www.vlsisymposium.org/wp-content/uploads/2026/05/VLSI26_Program_Finalv2.pdf - JFS5.4 A 28nm 0.7 pJ/bit Optically-Programmable, Fully-Digital SRAM-based Receiver Array with On-Chip
Session: Session JFS5: HPC Connectivity
https://www.vlsisymposium.org/wp-content/uploads/2026/05/VLSI26_Program_Finalv2.pdf - Session T15: Advanced Device Technology
https://www.vlsisymposium.org/wp-content/uploads/2026/05/VLSI26_Program_Finalv2.pdf - T15.1 Ultra Low-Power SRAM Technology on High Performance FinFET Platform for HPC, Mobile, and HighReliability Applications, Seunhan Park1, Yohwan Park1, Tae Hyung Kim1, Jinkyu Lee1, Hongjeon Kang1, Youngjae
Session: Session T15: Advanced Device Technology
https://www.vlsisymposium.org/wp-content/uploads/2026/05/VLSI26_Program_Finalv2.pdf - T15.2 10-nm-Gate-Length Nanosheet CNFET with Self-Aligned Extension Doping for Ambipolar Leakage
Session: Session T15: Advanced Device Technology
https://www.vlsisymposium.org/wp-content/uploads/2026/05/VLSI26_Program_Finalv2.pdf - T15.3 Interfacial-Layer-Free NCFETs Achieving 2mV Hysteresis, 27mV/dec SS, 2mV/V DIBL, and Record
Session: Session T15: Advanced Device Technology
https://www.vlsisymposium.org/wp-content/uploads/2026/05/VLSI26_Program_Finalv2.pdf - T15.4 Double-Flip Sequential CFET: Superior 3T Library Efficiency and PPA, Sheng Yang1, Jürgen Bömmels1,
Session: Session T15: Advanced Device Technology
https://www.vlsisymposium.org/wp-content/uploads/2026/05/VLSI26_Program_Finalv2.pdf - Session T16: Power Devices
https://www.vlsisymposium.org/wp-content/uploads/2026/05/VLSI26_Program_Finalv2.pdf - T16.1 First Demonstration of Ga2O3 Reverse Blocking Transistors with BV2/Ron,sp Figure-of-merit Over 1
Session: Session T16: Power Devices
https://www.vlsisymposium.org/wp-content/uploads/2026/05/VLSI26_Program_Finalv2.pdf - T16.2 6.5 kV Enhancement-Mode GaN Monolithic Bidirectional Switch (MBDS) Achieving Record Power
Session: Session T16: Power Devices
https://www.vlsisymposium.org/wp-content/uploads/2026/05/VLSI26_Program_Finalv2.pdf - T16.3 AlN Buffered K/Ku Bands GaN RF Power HEMTs with in-situ SiN Silicidation Enabled Low RC = 0.03
Session: Session T16: Power Devices
https://www.vlsisymposium.org/wp-content/uploads/2026/05/VLSI26_Program_Finalv2.pdf - T16.4 First demonstration of fmax > 700 GHz in Lg = 45 nm In0.13Al0.83Ga0.04N/GaN HEMTs for future 6G
Session: Session T16: Power Devices
https://www.vlsisymposium.org/wp-content/uploads/2026/05/VLSI26_Program_Finalv2.pdf - Session C28: Oversampled Noise Shaping ADCs
https://www.vlsisymposium.org/wp-content/uploads/2026/05/VLSI26_Program_Finalv2.pdf - C28.1 A 120-MHz BW CT 0-4 MASH DS ADC Employing a 2xTI SAR ADC and a Digital 1-0 MASH DSM DAC in
Session: Session C28: Oversampled Noise Shaping ADCs
https://www.vlsisymposium.org/wp-content/uploads/2026/05/VLSI26_Program_Finalv2.pdf - C28.2 A 1MHz-BW 90.1dB-SNDR CT Zoom ADC with Mismatch Error Shaping Preserving Full-Scale Input
Session: Session C28: Oversampled Noise Shaping ADCs
https://www.vlsisymposium.org/wp-content/uploads/2026/05/VLSI26_Program_Finalv2.pdf - C28.3 A 91.9dB-SNDR 100kHz-BW DT ΔΣ ADC Employing Thermal Noise Suppression Techniques with GainSwitched Dynamic Self-Quenching FIA, Ximing Wang1, Jiaao Yu1, Yunjie Chen1, Haoming Zhang1, Yuyang Zhu1,
Session: Session C28: Oversampled Noise Shaping ADCs
https://www.vlsisymposium.org/wp-content/uploads/2026/05/VLSI26_Program_Finalv2.pdf - C28.4 0.144mm2 Fully-Integrated-Onchip Fast-Converging Background Calibrations for 3-Stage 70.5dB-DR
Session: Session C28: Oversampled Noise Shaping ADCs
https://www.vlsisymposium.org/wp-content/uploads/2026/05/VLSI26_Program_Finalv2.pdf - C28.5 Robust Configurable 1.5MHz / 2.5MHz IF Quadrature CT ΔΣ Modulator Using SAQB and QDNC for 175.4
Session: Session C28: Oversampled Noise Shaping ADCs
https://www.vlsisymposium.org/wp-content/uploads/2026/05/VLSI26_Program_Finalv2.pdf - Session C29: Advanced Memory Design
https://www.vlsisymposium.org/wp-content/uploads/2026/05/VLSI26_Program_Finalv2.pdf - C29.1 A 2nm 37.4 Mbit/mm² Dual-Rail SRAM with Row-Access Aware Read Tracking and Write Assist Circuits
Session: Session C29: Advanced Memory Design
https://www.vlsisymposium.org/wp-content/uploads/2026/05/VLSI26_Program_Finalv2.pdf - C29.2 Dual-Phase Offset Compensation and Conditional Latch Gating for a Fully Single-Ended DRAM Core
Session: Session C29: Advanced Memory Design
https://www.vlsisymposium.org/wp-content/uploads/2026/05/VLSI26_Program_Finalv2.pdf - C29.3 A 25.3% Area-Efficient 1CPP Mask ROM with Robust Power Mesh on 2-nm NanoSheet Logic
Session: Session C29: Advanced Memory Design
https://www.vlsisymposium.org/wp-content/uploads/2026/05/VLSI26_Program_Finalv2.pdf - C29.4 A 2nm Nanosheet 128Kb Anti-Fuse One-Time-Programmable Memory Featuring Core-Transistor-Only
Session: Session C29: Advanced Memory Design
https://www.vlsisymposium.org/wp-content/uploads/2026/05/VLSI26_Program_Finalv2.pdf - C29.5 A 16 Mb 28 nm FD-SOI STT-MRAM Achieving 2.0 ns Read Access Time at 0.9 V via a PVT-VariationTolerant Dual-Reference Sensing Scheme, Youjin Choi1, Donguk Seo2, Mingyu Kim2, Heeyeon Kim1, Kyungjun
Session: Session C29: Advanced Memory Design
https://www.vlsisymposium.org/wp-content/uploads/2026/05/VLSI26_Program_Finalv2.pdf - Session JFS6: Power Management Devices & Design
https://www.vlsisymposium.org/wp-content/uploads/2026/05/VLSI26_Program_Finalv2.pdf - JFS6.1 Backside-Compatible Oxide Vertical Channel-All-Around Transistors and Cylindrical Capacitors for
Session: Session JFS6: Power Management Devices & Design
https://www.vlsisymposium.org/wp-content/uploads/2026/05/VLSI26_Program_Finalv2.pdf - JFS6.2 A 1.58-W/mm² Extreme-Power-Density Ka-Band GaN PA with Electro-Thermal-Mechanical Co-Design
Session: Session JFS6: Power Management Devices & Design
https://www.vlsisymposium.org/wp-content/uploads/2026/05/VLSI26_Program_Finalv2.pdf - JFS6.3 A 300mm Monolithic GaN MOSHEMT and Si pMOS Technology Demonstrating Energy-Efficient MultiThousand-Gate Digital Logic for Power Management, Samuel James Bader1, Heli Vora1, Po-Han Chen2, Saket
Session: Session JFS6: Power Management Devices & Design
https://www.vlsisymposium.org/wp-content/uploads/2026/05/VLSI26_Program_Finalv2.pdf - JFS6.4 A 4.8V 16nm Stackable Hybrid Fully Integrated Voltage Regulator with in-package Magnetic Inductors
Session: Session JFS6: Power Management Devices & Design
https://www.vlsisymposium.org/wp-content/uploads/2026/05/VLSI26_Program_Finalv2.pdf - Session T17: Advanced Packaging and 3D Integration
https://www.vlsisymposium.org/wp-content/uploads/2026/05/VLSI26_Program_Finalv2.pdf - T17.1 High-Density Chiplet Integration using Face-Down COW Processes with Bumpless Interconnects for
Session: Session T17: Advanced Packaging and 3D Integration
https://www.vlsisymposium.org/wp-content/uploads/2026/05/VLSI26_Program_Finalv2.pdf - T17.2 Record-High Power Dissipation (up to 5kW) Heterogeneous Integration Package with Direct-ChipsAttached Microfluidic Module Enabling TIM-Free Liquid Cooling , Yong Han1, Boon Long Lau1, Lai Yee Chia1,
Session: Session T17: Advanced Packaging and 3D Integration
https://www.vlsisymposium.org/wp-content/uploads/2026/05/VLSI26_Program_Finalv2.pdf - T17.3 An Upper-Tier ESD Protection Scheme Using Parallel-Electrode ITO TFTs for Monolithic-3D
Session: Session T17: Advanced Packaging and 3D Integration
https://www.vlsisymposium.org/wp-content/uploads/2026/05/VLSI26_Program_Finalv2.pdf - T17.4 High-Density Backside Connectivity with Remaining Bulk Silicon Substrate Using Self-Aligned Local
Session: Session T17: Advanced Packaging and 3D Integration
https://www.vlsisymposium.org/wp-content/uploads/2026/05/VLSI26_Program_Finalv2.pdf - T17.5 Multiple-Wafer (9-layer), Extreme thin (3µm-Si per stack) and Innovative Fusion-bonded Via-in-one
Session: Session T17: Advanced Packaging and 3D Integration
https://www.vlsisymposium.org/wp-content/uploads/2026/05/VLSI26_Program_Finalv2.pdf - Session T18: Memories for AI Applications
https://www.vlsisymposium.org/wp-content/uploads/2026/05/VLSI26_Program_Finalv2.pdf - T18.1 A 4Mb 3bits/cell RRAM Macro in 12nm FinFET Technology with the smallest 0.019μm2Bit-cell, 100Kcycle Endurance and 10 years Retention up to 125oC, Yuan He1, Kaimeng Liu1, Jianshi Tang1, Cong Sun1, Wei
Session: Session T18: Memories for AI Applications
https://www.vlsisymposium.org/wp-content/uploads/2026/05/VLSI26_Program_Finalv2.pdf - T18.2 Monolithic 3D Integration of Stacked IGZO/Si Memtransistor-based 2T0C Gain Cell for Attention
Session: Session T18: Memories for AI Applications
https://www.vlsisymposium.org/wp-content/uploads/2026/05/VLSI26_Program_Finalv2.pdf - T18.3 First Demonstration of Heterogeneous n-IGZO/p-WSe2 Integration as a Power-Performance-Area
Session: Session T18: Memories for AI Applications
https://www.vlsisymposium.org/wp-content/uploads/2026/05/VLSI26_Program_Finalv2.pdf - T18.4 FAB Gain Cell Memory: A Folded Asymmetric Boosted Design to Improve Sense Margin for a RefreshFree Operation, Jay Sonawane1, Sunbin Deng1, Kiseok Lee1, Faaiq Waqar1, Chengyang Zhang1, Omkar Phadke1,
Session: Session T18: Memories for AI Applications
https://www.vlsisymposium.org/wp-content/uploads/2026/05/VLSI26_Program_Finalv2.pdf - T18.5 Vertically stacked Five-Word-Line IGZO FeFETs with Dual-Gate-Enabled Stable Erase Toward HighBandwidth Storage, Zhuo Chen1,2, Nicolò Ronchi1, Roman Izmailov1,2, Kruti Trivedi1, Subhali Subhechha1, Devin
Session: Session T18: Memories for AI Applications
https://www.vlsisymposium.org/wp-content/uploads/2026/05/VLSI26_Program_Finalv2.pdf - Session T19: Imagers, Sensors and RF Devices
https://www.vlsisymposium.org/wp-content/uploads/2026/05/VLSI26_Program_Finalv2.pdf - T19.1 A Single Exposure 137 dB Dynamic Range CMOS Image Sensor with Low Dielectric Absorption Image
Session: Session T19: Imagers, Sensors and RF Devices
https://www.vlsisymposium.org/wp-content/uploads/2026/05/VLSI26_Program_Finalv2.pdf - T19.2 A fully-buried transfer gate and polysilicon wire: Noise enhancement technology for CMOS image
Session: Session T19: Imagers, Sensors and RF Devices
https://www.vlsisymposium.org/wp-content/uploads/2026/05/VLSI26_Program_Finalv2.pdf - T19.3 Record-Performance In2O3 FETs with Ultra-scaled Contacted Gate Pitch: Enabled by Higher-k HZO
Session: Session T19: Imagers, Sensors and RF Devices
https://www.vlsisymposium.org/wp-content/uploads/2026/05/VLSI26_Program_Finalv2.pdf - T19.4 First Demonstration of High-precision (15 bits) Photonic-electronic Hybrid Compute-in-memory
Session: Session T19: Imagers, Sensors and RF Devices
https://www.vlsisymposium.org/wp-content/uploads/2026/05/VLSI26_Program_Finalv2.pdf - T19.5 Monolithic Photonic BiCMOS Technology with 400-GHz SiGe-HBTs and Germanium-Fin
Session: Session T19: Imagers, Sensors and RF Devices
https://www.vlsisymposium.org/wp-content/uploads/2026/05/VLSI26_Program_Finalv2.pdf
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