2026 06 14 Feed Semianalysis Smic N3 Metal Pitch VS Intel 18A

Summary

SemiAnalysis's STEEL teardown lab reverse-engineered the HiSilicon Kirin 9030 Pro (SMIC N+3) and finds SMIC's minimum metal pitch (32.5 nm) is actually ~10% tighter than Intel 18A (36 nm) — but frames this as a cherry-picked metric, not overall process superiority. The load-bearing causal claim: without EUV, SMIC compensates with aggressive DUV multi-patterning (self-aligned quadruple patterning, SAQP, for M0) and design-technology co-optimization to reach ~TSMC N6-class logic density (113.4 MTr/mm²), but at the cost of higher complexity, reduced process margins, and limited further scaling — which is pushing Huawei toward 3D "LogicFolding" (vertically stacking active logic dies at ultra-fine pitch) and system-technology co-optimization (the "τ/tau" roadmap) as the primary path forward. Export-control context: EDA-tool restrictions forced domestic Chinese tool development (Peking University LogicFolding prototypes; diffusion across HLMC / Hua Hong).

Relevance to the book: bears on Intel 18A's competitive positioning (us-fab-capacity-bottleneck, tsmc-saturation-to-intel-anchor-stack), the efficacy/limits of US export controls (china-ree-controls-to-us-producer-stack inverse — controls as a forcing function), and the China-fab-capability question underneath the Taiwan-chokepoint reshoring thesis (taiwan-chokepoint-to-allied-reshoring).

Article

⚠ partial / paywalled — SemiAnalysis gates the full teardown behind a paid subscription. The text below is the free-portion summary as rendered by the publisher's own preview; the detailed process tables, die shots, and roadmap section are behind the paywall. Cite as a partial source.

Publication: SemiAnalysis (Substack newsletter). Author: STEEL Team — Afzal Ahmad, Andrew Wagner, and others. Date: June 14, 2026.

The piece opens with its headline question on metal-pitch comparison, then explains that while SMIC N+3 achieves a 32.5 nm minimum metal pitch — roughly 10% tighter than Intel's 18A at 36 nm — this is a "cherry picked metric" rather than evidence of overall superiority.

The report details SemiAnalysis's new STEEL teardown laboratory in Oregon and presents findings from reverse-engineering the HiSilicon Kirin 9030 Pro SoC and the MediaTek Helio G99 for comparison. Key findings include architectural analysis showing incremental improvements in CPU cores, GPU enhancements with ray-tracing support, and restructured NPU configurations.

The process analysis reveals SMIC N+3 uses aggressive DUV multi-patterning with self-aligned quadruple patterning (SAQP) for M0 layers at 32.5 nm pitch. Fin profiles are "taller, narrower and less rounded" than TSMC N6, with an aspect ratio of 9.5:1 versus 7.8:1. Standard cell height measures 228 nm with transistor density of 113.4 MTr/mm².

Memory specifications include Samsung LPDDR5X-9600 dies on Samsung's 1a process. Packaging uses integrated package-on-package (iPoP) stacking with organic redistribution layers rather than silicon interposers.

The roadmap section outlines Huawei's τ (tau) scaling approach emphasizing "system-technology co-optimization" through LogicFolding — vertically stacking active logic dies at ultra-fine pitch to shorten critical paths and reduce buffering overhead beyond what planar density scaling allows.

Export-controls context explains how EDA-tool restrictions forced development of domestic Chinese tools, with Peking University creating prototypes for LogicFolding architectures, and knowledge diffusing across fabs like HLMC / Hua Hong.

Primary causal argument (publisher's framing): Without access to EUV lithography, SMIC compensates through aggressive DUV multi-patterning and design-technology co-optimization to reach comparable logic density to TSMC N6, but this approach increases complexity, reduces process margins, and limits further scaling — prompting Huawei toward 3D stacking and system-level optimization as the primary path forward.