Autoresearch: Intel 18A VLSI / yield follow-up vs TSMC

Generated by /autoresearch on 2026-08-21. Synthesized across 3 rounds from 13 web pages (plus 1 thin Tom's Hardware extract), anchored by Intel 18A. See Provenance. Treat as raw material — review before promoting into a project or thread. Context: vault/projects/stock-market Prompt: the open question on intel-18a-yield-vs-tsmc — Has Intel 18A reached yield parity with TSMC, or are partnerships outpacing the technical reality? Scope is the uningested VLSI June 14–18 catalyst, peer-reviewed 18A-P vs TSMC A16, and Panther Lake / IFS Q2 yield primaries. Not a re-run of the May partnership tape.

Summary

The June 2026 VLSI symposium delivered the promised PPA papers — Intel 18A-P vs base 18A, TSMC A16 vs N2P — and did not publish a die-yield comparison. Intel's own Q2 2026 primaries say 18A output and cost improved (primary Panther Lake SKU cost down ~50% year-to-date; output ~25% above target and up more than 50% quarter-over-quarter) but still give no numeric yield percentage, and the 10-Q still calls 18A wafers a higher-cost mix. The only post-June 85% / TSMC-N2-90% comparison is KeyBanc supply-chain modeling — the same firm that produced the mid-2025 ~55% figure the question already flagged as not Intel-disclosed. External foundry revenue was $293 million against $5.8 billion Foundry, and the 10-Q says that external line is still mostly Altera-after-deconsolidation plus other third-party work, not a disclosed 18A merchant book. Partnerships remain ahead of shipped external 18A silicon.

Findings

VLSI 2026 published PPA, not yield

The 2026 IEEE/JSAP Symposium on VLSI Technology and Circuits ran in Honolulu; the Technology Highlights session that held both papers was Tuesday, June 16 (Intel T1.2 session page; TSMC T1.5 session page).

Intel paper T1.2 (Anupama Bowonder et al., Intel Foundry) describes 18A-P as a performance-enhanced RibbonFET + PowerVia node that is design-compatible with 18A. The official abstract: "over 18% lower power at iso-performance, or over 9% performance gain at iso-power," via additional logic VT pairs, skew-corner tightening, new HD/HP low-power and high-performance devices, and reduced thermal resistance (T1.2 abstract). Intel's June 16 newsroom restates those same PPA numbers and adds: 18A-P is in risk production; Power Boost dual-contact transistors; 20–40% improved thermal resistance; 10–30% improved via resistance; a new fifth logic Vt pair between ULVT and LVT; two cell heights (180 nm and 160 nm) and a 50 nm contacted poly pitch, same as 18A (Intel Foundry VLSI newsroom, 2026-06-16). The same release reports invited-talk numbers on the already-shipping 18A stack: Eric Karl claimed 11% routed-area reduction and 10× dynamic voltage-droop reduction versus a comparable frontside interconnect, enabling up to 6% frequency uplift or greater than 15% dynamic power reduction; Manju Shamanna claimed ~30% frequency improvement at ~0.5 V on GAA + backside-power CPU-core silicon (same Intel newsroom). No die-yield, defect-density, or 18A-vs-N2 yield figure appears in the abstract or the newsroom.

TSMC late-news paper T1.5 (Geoffrey Yeap et al.) is the A16 platform with Super Power Rail (SPR) backside direct contact. The official abstract: A16 is "developed and qualified"; vs N2P it is "8%~10% faster speed at power, or 15%~20% power improvement and additional 8%~10% chip density gain"; mass production "slated for Q4'26" (T1.5 abstract). SemiWiki's post-symposium write-up restates those abstract numbers and notes SPR is meant to preserve N2P gate density and NanoFlex DTCO; it does not add a yield number (SemiWiki, TSMC A16 at VLSI 2026). This is a same-family PPA delta (A16 vs N2P), not a head-to-head 18A-P vs A16 yield or density bake-off. The two papers sit in the same session; they do not share a common test vehicle in the public abstracts.

Intel's Q2 10-Q independently dates 18A-P risk production to June 2026 (Intel Form 10-Q for the quarter ended June 27, 2026).

IFS Q2 primaries: cost and output moved; no disclosed yield %

Intel's July 23, 2026 Q2 release: revenue $16.1 billion (+25% YoY); Foundry $5.8 billion (+31% YoY); CFO Dave Zinsner attributed volume upside to "higher factory yields and improved cycle times" without a percentage (Intel Q2 2026 earnings release). Foundry highlights in that release: 18A-P entered risk production; a subset of Core Ultra Series 3 (Panther Lake) is in high-volume manufacturing using ASML EXE High NA EUV; Xeon 6+ (Clearwater Forest) is Intel's first server-class 18A product (same release).

On the earnings call, Tan: factories on Intel 7, Intel 3, and 18A "exceeded internal volume targets, driven by improving yields, better cycle times, and increasing wafer starts"; "18A output increased meaningfully"; "Yields continue to track ahead of expectations"; 18A is in volume production across multiple commercial and consumer products and factory output "continues to increase sequentially every month" (stockanalysis.com Q2 2026 transcript). Zinsner: Foundry revenue $5.8 billion, up 6% sequentially, "driven by strong growth in Intel 18A, with output approximately 25% above target and up more than 50% quarter-over-quarter"; external foundry revenue $293 million; Foundry operating loss $2.1 billion, $348 million better QoQ, "as higher yields, improved cycle times and increased factory scale across Intel 4, Intel 3, and 18A drove improved wafer costs"; "Intel Foundry has driven down the cost of our primary Panther Lake SKU by roughly 50% year-to-date and is on track for an additional 20% this year, with further meaningful reductions planned in 2027"; Q3 quarter-to-date 18A yields "trending ahead of targets set in March" (same transcript).

The 10-Q is the harder primary. External (third-party) foundry and assembly/test revenue was $293 million in the three months ended June 27, 2026 and $467 million in the first six months ($22 million and $53 million in the year-ago periods). The filing says Foundry revenue "consists substantially of intersegment" sales to Intel Products, and that "at present, substantially all of our Intel Foundry business supports internal manufacturing for Intel Products" (Intel 10-Q). It also attributes the YoY jump in external revenue "primarily due to Altera's transition to an external customer following the deconsolidation of Altera in Q3 2025" — so the $293 million is not a disclosed 18A merchant-wafer run-rate (same 10-Q). Foundry operating loss was $2.1 billion in Q2. Product profit was hurt by "an increased mix of higher-cost wafers manufactured on our Intel 18A process node," which "substantially offset higher revenue and lower wafer costs on Intel 3 and Intel 4" (same 10-Q). That is the opposite of a filed claim that 18A has reached cost parity.

Intel still does not disclose an 18A die-yield percentage in the release, the call, or the 10-Q.

The 85% figure is still KeyBanc, not Intel and not a teardown

On or about July 15, 2026, KeyBanc's John Vinh published a supply-chain note that 18A yields "improving to 85% from 65% in the previous quarter," still trailing "TSMC's N2 yields of 90%" and "meaningfully above Samsung Foundry SF2 yields of 50-60%" (quoted in Mark Lapedus / via search reprint of the Vinh note; the same 65%→85% / TSMC ~90% / SF2 50–60% triad is in TechTimes, 2026-07-15). TechTimes is explicit that the 85% "milestone" is "reported … by KeyBanc Capital Markets" and that KeyBanc raised its INTC target from $110 to $155 on the back of it (TechTimes). RCRTech repeats the same KeyBanc numbers and immediately caveats: the figures "may be based on specific product types or internal test chips," a reticle-sized AI die is "a very different animal from a Panther Lake CPU tile," and "high-volume external 18A parts aren't shipping yet; current 18A output primarily supports Intel's own Panther Lake CPUs" (RCRTech, 2026-07-20).

This is the same modeling channel (KeyBanc) that produced the mid-2025 ~55% estimate the question page already treats as not Intel-disclosed and not third-party verified. This pass found no SemiAnalysis teardown and no Tom's Hardware die-yield number that independently confirms 85% or TSMC N2 90%. A Tom's Hardware 18A-P risk-production story exists (URL) but the fetch returned only comment fragments ("Intel says that defect rates continue to drop along with its expectations") — treat as thin, not as a yield table.

A separate sell-side note from BlueFin Research Partners, as retold by TechSpot, says 18A yield issues are "resolved" enough for economically sustainable HVM and that defect density has "likely reached the lower end" of a mature-node D0=0.1–0.2 range; it puts combined Fab 52 (Phoenix) + Hillsboro output at about 30,000 wafers per month, "currently sufficient to meet Intel's internal demand" and "focused on Intel's own products"; 18A-P risk production is at D1X (Oregon), with later HVM planned at Fab 62 (TechSpot / BlueFin). BlueFin is also not a wafer teardown. D0≈0.1 is a defect-density claim, not a die-yield percentage, and it is attributed as "likely."

ASML High NA is a litho-layer claim, not an 18A-vs-N2 yield claim

ASML's July 15, 2026 press release: Intel Foundry is using EXE High NA EUV on the 18A node for a subset of Core Ultra Series 3 (Panther Lake); "specific Intel 18A layers are now dual-qualified on High NA EUV in Oregon, with product shipping to customers at yields matched to the NXE platform" (ASML, 2026-07-15). That is a tool-to-tool (High NA vs low-NA EUV) layer-yield match on selected layers of a subset of SKUs — not a die-yield versus TSMC N2, and not a claim that Panther Lake is a High-NA-throughout chip. Intel's Q2 release repeats the same subset/HVM wording (Intel Q2 release).

TSMC N2 is in revenue; TSMC did not publish an N2 yield %

TSMC's own Q2 2026 earnings release (SEC HTML): 2-nanometer accounted for 3% of wafer revenue in Q2 2026 (0% in Q1 2026 and Q2 2025); 3 nm 30%, 5 nm 33%, 7 nm 11%; advanced (7 nm and below) 77% of wafer revenue. Wendell Huang: Q3 will include "the steep ramp-up of our 2-nanometer technology." Q2 revenue $40.20 billion; gross margin 67.7% (TSMC Q2 2026 earnings release on SEC). The VectorShift HTML transcript of the July 16 call adds: inventory days rose to 87 "primarily due to the ramp of N2 technology"; Q3 gross-margin guide 65–67% (midpoint down ~1.7 points) because the "steep N2 ramp is expected to dilute" 2H gross margin by about 3–4 points (VectorShift TSMC Q2 2026 transcript). The same transcript's A14 development vehicle is "close to 90% device performance and close to 90% 256 Mb SRAM yield" — that is A14 R&D, not N2 HVM yield, and not A16 (same transcript). TSMC did not disclose an N2 or A16 volume-production die-yield percentage in the fetched Q2 materials. A16 mass production remains the VLSI abstract's Q4'26 slate (T1.5); it is not yet a revenue node in the Q2 mix.

KeyBanc's "TSMC N2 ~90%" is therefore also modeled, not a TSMC primary.

18A-P "5%" vs VLSI "9% / 18%" is unresolved

On the Q2 call Tan said 18A-P "is in the risk production now and will be ready before the end of this year. Clearly, we see an enhanced performance of around 5% versus 18A" (stockanalysis transcript). That verbal ~5% does not match the June 16 newsroom / T1.2 abstract of 9% iso-power or 18% iso-performance. Do not collapse them. Possible (unverified) readings: different vehicles, a product-level vs process-level metric, or a misspeak. The citable official paper number remains the VLSI/newsroom pair; the citable CEO verbal number is ~5%. Neither is a yield number.

What this does not settle about partnerships

This pass did not re-litigate the May Apple / Microsoft / AWS tape. Q2 primaries still do not name an external 18A volume customer. The 10-Q is explicit that Foundry is still substantially internal and that the $293 million external line is primarily the Altera deconsolidation plus other third-party foundry/OSAT work (Intel 10-Q). KeyBanc's July roster of reported design wins (Apple, AMD, Nvidia, etc.) is the same sell-side channel as the 85% yield figure; RCRTech flags those names as "reportedly" / hedges, not confirmed production (RCRTech). Treat that roster as unconfirmed.

Grokipedia's Intel 18A primer (fetched 2026-08-21) still frames yields as "progressing toward industry standards by 2027" and notes High-NA / Panther Lake HVM as of early 2026 — useful vocabulary, not a yield table (Grokipedia: Intel 18A).

Contradictions and open questions

• VLSI did not answer the yield question. The named June 14–18 catalyst produced peer-reviewed PPA (18A-P vs 18A; A16 vs N2P). It did not produce an 18A-P vs A16 yield, defect-density, or common-vehicle bake-off in the public abstracts or Intel's newsroom.
• 85% vs "higher-cost 18A wafers." KeyBanc's 85% (and the implied near-parity with a modeled TSMC N2 90%) sits next to Intel's 10-Q language that 18A wafers are still a higher-cost mix dragging Foundry product profit. Those can both be true (yield up, still not at Intel 3/4 cost; or 85% on a small tile vs cost on the mix), but they are not the same claim. Do not treat 85% as filed.
• Tan ~5% vs VLSI +9% / −18%. Unresolved. Cite both; do not average them.
• BlueFin D0≈0.1 vs KeyBanc 85% vs Intel "ahead of expectations." Three different rulers (defect density, modeled % yield, qualitative vs internal plan). No public conversion.
• External 18A silicon. Still not in the $293 million in any disclosed way. High-volume 18A remains Intel's own Panther Lake / Wildcat Lake / Xeon 6+ stack.
• TSMC N2 yield. Not disclosed. 3% of wafer revenue plus a guided GM dilution from a "steep" ramp is the primary. KeyBanc's 90% is not a TSMC number.
• Still missing: SemiAnalysis or AnandTech/Tom's Hardware wafer-level yield on Panther Lake; time-to-revenue terms on any named 18A foundry deal; an IEEE Xplore full-paper table (PDFs were out of fetch scope).

Provenance

Rounds run: 3 of 3

Sub-questions by round:

Round 1 (broad survey):

1. What did VLSI 2026 actually publish for Intel 18A-P vs TSMC A16?
2. What quantitative 18A / Panther Lake yield numbers appeared after June 1, 2026?
3. What did Intel say on IFS Q2 2026 about 18A yield, Panther Lake ramp, and foundry revenue?
4. How does TSMC N2 / A16 yield and production status compare as of mid-2026?

Round 2 (drill-down):

1. What did TSMC actually publish at VLSI for A16 after June 14–18? — targeting the April tipsheet vs post-symposium paper
2. Can KeyBanc's 85% / TSMC ~90% be independently corroborated? — targeting the same-firm problem as the original 55%
3. How to reconcile Tan's Q2 "~5%" with VLSI +9%/18%? — targeting the PPA contradiction
4. What does TSMC Q2 HTML commentary say about N2 ramp and A16 timing? — targeting a TSMC primary without fetching off-whitelist PDFs

Round 3 (resolve remaining uncertainty):

1. Does Intel's Q2 10-Q give a numeric 18A yield? — targeting a filed number
2. What does TSMC's Q2 HTML transcript add on N2 / A16 / yield? — targeting TSMC's own words

Anchor source (Grokipedia, fetched before round 1):

• Intel 18A — 25,017 chars extracted — process definition (RibbonFET, PowerVia, Panther Lake HVM, industry-standard yields framed as 2027). Encyclopedic primer; not used as a yield primary.

URLs fetched (13 successful, 1 thin):

Round 1:

• Intel Foundry Details Process Milestones and Future Innovation at VLSI Symposium — official — 18A-P risk production; +9% / −18%; thermal and via-resistance figures; Karl / Shamanna invited-talk numbers. No yield %.
• Intel Reports Second-Quarter 2026 Financial Results — official IR — $16.1B / Foundry $5.8B; High NA subset; 18A-P risk production; Xeon 6+ on 18A.
• Intel (INTC) Q2 2026 Earnings Call Transcript — transcript reprint — Tan/Zinsner yield-ahead, +25% / +50% 18A output, $293M external, −50% PTL SKU cost, Tan ~5% 18A-P.
• Intel Foundry Hits 85% Yield… — news (KeyBanc retell) — 65%→85%; TSMC N2 ~90%; SF2 50–60%; KeyBanc $155 PT. Not a primary yield.
• VLSI T1.2 session — Intel 18A-P — official program — peer-reviewed abstract; PPA only.
• ASML: High NA EUV reaches new readiness milestone — official — subset of Panther Lake layers; yields matched to NXE, not to TSMC.

Round 2:

• VLSI T1.5 session — TSMC A16 — official program — +8–10% speed / 15–20% power / 8–10% density vs N2P; MP Q4'26; no yield.
• TSMC A16 Backside Power at VLSI 2026 — specialist press — restates T1.5 abstract; SPR / NanoFlex; no added yield.
• TSMC Reports Second Quarter (SEC HTML) — official / SEC — N2 = 3% of wafer revenue; steep Q3 N2 ramp; no N2 yield %.
• Intel Foundry 18A yields jump… — news (KeyBanc retell) — same 85/90/50–60 triad; useful caveats on die size and external HVM.
• Intel's troubled 18A chip process is finally running smoothly — news (BlueFin retell) — qualitative "resolved"; D0 "likely" 0.1; ~30k wpm internal-focused.

Round 3:

• TSMC Q2 2026 earnings call (VectorShift HTML) — transcript reprint — N2 GM dilution 3–4 pts; inventory days 87 from N2 ramp; A14 vehicle ~90% SRAM yield (not N2).
• Intel Form 10-Q, quarter ended June 27, 2026 — official / SEC — $293M external (primarily Altera + other third-party); 18A-P risk production June 2026; 18A wafers still higher-cost; no yield %.
• Thin extract: Tom's Hardware 18A-P risk production — fetch returned comment fragments only.

Not fetched (PDF, off whitelist): VLSI 2026 program PDF and April 25 tipsheet PDF on vlsisymposium.org. Public HTML session abstracts + Intel newsroom used instead.

Tools used: WebSearch, WebFetch, grokipedia-fetch (skill / _lib/grokipedia.py). Generated: 2026-08-21 14:10 UTC