TSMC packaging scarcity caps customer growth → strands TSMC's own (larger) front-end wafer revenue → incumbent welcomes a second-source packager → Intel EMIB-T demand is validated by the monopolist itself

The wiki's May read treated Intel's EMIB-T as a mild headwind for TSMC's CoWoS franchise. C.C. Wei inverts it on the record: packaging scarcity is capping his customers' growth and therefore stranding TSMC's front-end wafer revenue — which is 'a majority part of TSMC's business.' He does not defend the packaging franchise; he welcomes a competitor taking load off it, because back-end share is worth less than the front-end wafer revenue sitting behind the packaging gate. A supplier conceding a bottleneck against interest both confirms the constraint and validates the second-source demand.

• Step 1: TSMC discloses advanced-packaging utilisation below 100%, or Wei/Huang state on a later call that the packaging gap has closed.
• Step 2: TSMC's platform mix shifts such that front-end wafer is no longer the majority of revenue, or TSMC reports front-end growth unconstrained by packaging.
• Step 3: TSMC reverses posture and moves to defend packaging share — bundling front-end wafer with in-house packaging, or refusing to ship wafer destined for a competitor's package.
• Step 4: Hyperscaler ASICs stay on CoWoS; TSMC brings outsourced CoWoS steps back in-house and stops using AMKR/ASE overflow.
• Step 5: Intel discloses EMIB-T volumes that are immaterial, or loses a named packaging customer back to TSMC — which would leave the demand validated but uncapturable and retire the INTC leg.

• **Step 5 is the tradeable step and it is `open`.** Wei validates that a second source is *wanted*; nothing here shows Intel *winning* it, at what volume, or at what margin. A validated demand pool that Intel fails to convert (on yield, capacity, or qualification timelines) pays nothing.
• **Wei's 'welcome' is cheap talk in one reading.** A monopolist publicly welcoming a competitor costs nothing and buys goodwill with customers and regulators. The against-interest framing is strong but not airtight — he is also managing an antitrust-adjacent narrative and a customer base angry about allocation.
• **This inverts the wiki's own prior read, logged 2026-05-19.** 2026-05-19-autoresearch-cowos-packaging-capacity-may-2026-update treated the CoWoS→EMIB ASIC migration as 'simultaneously a mild headwind for CoWoS and a tailwind for the Intel thesis.' That read priced the packaging revenue TSMC might lose and ignored the larger wafer revenue TSMC cannot currently bill. The May framing is superseded on the TSM side; the INTC side survives and strengthens.
• **TSMC's packaging capex is deliberately not separable**, so the constraint cannot be tracked externally. cc-wei declined Goldman's request to break it out: "Sometimes we have a bottleneck, we put more money to buy the bottleneck tools, sometimes it's in the front end, sometimes it's in the back end." The fungibility is real, but it also means there is no public series to falsify step 1 against.
• **Relief valves exist and are dated ~1 year out.** Wei on the glass-substrate alternative: "it will take about another one year to be mature so we can put it into the production with our customer." If TSMC's own alternatives mature, the second-source demand narrows.
• **A live no-CoWoS architecture exists** — Cerebras's wafer-scale approach uses no CoWoS at all, so the packaging bottleneck is a constraint on the GPU/chiplet architecture specifically, not a universal one. See inference-demand-to-wafer-scale-advantage.

• **INTC — a packaging leg independent of the foundry leg.** The existing Intel thesis (tsmc-saturation-to-intel-anchor-stack) routes through front-end wafer: TSMC saturation → price hikes → anchor customers commit to 18A/14A. This is a *different* intermediate reaching the same ticker: Intel's back-end (EMIB-T) has demand pull because the incumbent's packaging is the binding gate and the incumbent has publicly said so. The two legs can pay off independently — and EMIB-T does not depend on 18A/14A yield.
• **TSM — the read flips from headwind to tailwind.** Third-party packaging relief unlocks front-end wafer revenue TSMC currently cannot bill. Packaging share loss is a *good trade* for TSM at these gaps, because the stranded pool is larger than the defended one.
• **OSAT overflow is the corroborating expression** — AMKR and ASE already receive TSMC CoWoS outsourcing on a persistent 15-20% gap. See cowos-packaging-capacity-crunch.
• **Watch: Intel's next earnings call for EMIB-T volume/customer disclosure.** That is the single datum that would move step 5 from `open` to evidenced.