CoWoS packaging capacity crunch
CoWoS packaging capacity crunch
One-line summary: Nvidia is consuming >50% of TSMC's total CoWoS (Chip-on-Wafer-on-Substrate) packaging capacity, creating a second supply bottleneck on top of the leading-edge logic foundry constraint — advanced packaging equipment makers (BESI, AMAT, ASE) benefit regardless of which GPU wins.
The insight
Leading-edge silicon is only part of the AI chip supply chain. After wafers are fabricated, HBM is bonded to logic dies through advanced packaging processes (CoWoS, SoIC, 3D stacking). Nvidia's GPU + HBM modules require CoWoS, and Nvidia's scale means it monopolizes TSMC's CoWoS capacity. This is an independent bottleneck from logic lithography and from raw HBM supply — it is the integration constraint.
Advanced packaging equipment is the picks-and-shovels play on this bottleneck: BESI (bonder equipment), AMAT (packaging tools), and ASE (OSAT assembly) all benefit as packaging capacity must expand.
The chain
TSMC CoWoS 50%+ consumed by Nvidia → AMD, Broadcom, Google TPU compete for remainder → packaging is the binding bottleneck for non-Nvidia accelerators; TSMC captures continued packaging revenue even as wafer fab is shared.
Canonical: hbm-cowos-as-binding-bottleneck.
Evidence
- From 2026-05-11-autoresearch-macro-semis-ai-infrastructure-may-2026: Nvidia consuming >50% of TSMC's total CoWoS capacity with 800–850K wafers/year. This level of concentration means any other customer needing CoWoS (AMD, Broadcom, others) faces a queue behind Nvidia.
- From 2026-05-11-autoresearch-picks-shovels-semicap-update-may-2026: Lam Research launched "Vector Teos 3D" to compete with AMAT in advanced packaging — the competitive entry confirms the market opportunity is large enough to attract a new tool entrant.
- From 2026-05-11-autoresearch-macro-semis-ai-infrastructure-may-2026: CoWoS backlog through 2026 is cited as a direct constraint on Nvidia shipment velocity — packaging, not just logic yield, is gating AI system delivery.
- From 2026-05-19-autoresearch-cowos-packaging-capacity-may-2026-update: TSMC May 14, 2026 Technology Symposium: CoWoS yield >98% on the 5.5-reticle-size CoWoS solution (largest chip-on-wafer ever produced at volume, supporting 12 HBM chips per package). Third-generation CoWoS volume production started 2026 (12 HBM stacks, up from 8).
- From 2026-05-19-autoresearch-cowos-packaging-capacity-may-2026-update: TSMC CoWoS target: 130,000 wafers/month by late 2026 (from ~35,000 WPM in late 2024 — nearly 4x in ~24 months). CoWoS + SoIC capacity CAGR: >80%/year through 2027. 5 new fabs coming online in 2026.
- From 2026-05-19-autoresearch-cowos-packaging-capacity-may-2026-update: Despite 4x capacity expansion, analysts expect only "slight easing" in supply-demand gap by 2027 — demand is growing at least as fast as supply. NVIDIA alone books ~60% of all CoWoS capacity (estimated 595,000 wafers in 2026), with advanced packaging lines booked "several years ahead."
- From 2026-05-19-autoresearch-cowos-packaging-capacity-may-2026-update: TSMC outsourcing to ASE and Amkor due to persistent 15-20% supply-demand gap — clearest signal TSMC cannot close the gap through internal expansion alone.
- From 2026-05-19-autoresearch-cowos-packaging-capacity-may-2026-update: BESI Q1 2026 results: revenue €184.9M (+28.3% YoY); orders €269.7M (more than doubled YoY, driven by hybrid bonding); backlog ~€400M; Q2 guidance +30-40% sequential (new record ~€240-260M); gross margin 64-66%. Needham named BESI Top Pick on HBM hybrid bonding thesis. 12-18 month lead times for hybrid bonders = Q1 orders → Q3-Q4 revenue.
- From 2026-05-19-autoresearch-cowos-packaging-capacity-may-2026-update: ASE Technology doubling advanced packaging sales to $3.2B in 2026; bought NT$2.8B Zhunan facility; serving NVIDIA, AMD, and others; projected to exceed 200,000 wafers by 2027; "likely to be primary beneficiary" of TSMC outsourcing.
- From 2026-05-19-autoresearch-cowos-packaging-capacity-may-2026-update: EMIB signal: TrendForce notes ASICs from hyperscalers are expected to shift from CoWoS to EMIB (Intel's Embedded Multi-die Interconnect Bridge). If Intel 18A packages with EMIB at scale, some ASIC demand could route around TSMC's CoWoS — simultaneously a mild headwind for CoWoS and a tailwind for the Intel thesis.
- From 2026-05-20-autoresearch-tsmc-capacity-pricing-power-n2-cowos-may-2026: CoWoS fully sold through 2027 per TSMC Q1 2026 earnings call (April 17, 2026). Management has aggressively built CoWoS capacity and packaging-focused fabs; Q2 2026 guidance implies continued strong CoWoS revenue contribution. 50+ week lead times as of Q1 2026.
- From 2026-05-25-autoresearch-tsmc-capacity-shortfall-may-2026-update: Nvidia securing ~60% of total global CoWoS demand (595K wafers booked 2026). TSMC outsourcing CoWoS steps to ASE AND Amkor Technology (AMKR) due to persistent 15-20% supply-demand gap.
- From 2026-05-26-autoresearch-amkr-cowos-advanced-packaging-q1-2026: AMKR Q1 2026 record $1.68B revenue (+27% YoY); AI advanced packaging guided to triple in 2026; HDFO platform (CoWoS-equivalent) has 5+ customers in qualification. Global CoWoS demand reaching ~1M wafers/year in 2026. Graduation criteria for amkor-cowos-tsmc-overflow-osat substantially met — AMKR added to suggested-tickers. Mechanism note: Amkor is both TSMC CoWoS overflow receiver AND independent HDFO platform vendor (SWIFT = CoWoS-R equivalent; S-Connect = CoWoS-L equivalent).
- From 2026-05-26-autoresearch-semis-ai-infra-macro-scan-may-23-26-2026: CoWoS ASP approaching $10,000/wafer — parity with 7nm advanced logic nodes (TrendForce, April 2026). TSMC CoWoS roadmap: current = 5.5-reticle-size; 2028 = 14-reticle-size CoWoS packages; 2029 = 48x compute leap, supporting 24 HBM5E stacks per package. This roadmap extends the packaging bottleneck thesis well beyond 2027 — each new generation requires new equipment investment. Nvidia Feynman (2028) expected to use HBM5, not HBM4.
- From 2026-05-29-autoresearch-cowos-nvidia-150b-taiwan-may-29: Nvidia $150B/year Taiwan pledge (announced Computex, May 27-28, 2026). Jensen Huang called Taiwan "the epicentre of the AI revolution." Nvidia Constellation Campus breaking ground June/July 2026, operations targeted 2030. During his Taiwan visit (May 23), Huang met TSMC Chairman C.C. Wei specifically to discuss Vera Rubin production commitments — the conversation was explicitly about packaging capacity for the next-generation platform.
- From 2026-05-29-autoresearch-cowos-nvidia-150b-taiwan-may-29: Vera Rubin six-die architecture adds fresh CoWoS demand. Vera Rubin is a six-chip multi-die system requiring more CoWoS interposer area per unit than GB300. TSMC must simultaneously ramp CoWoS for GB300 tail production while starting Vera Rubin front-end ramp — straining an already-oversubscribed line. Huang: Vera Rubin is "the most successful product generation in Nvidia's history" and "the biggest product ramp in computer history."
- From 2026-05-29-autoresearch-cowos-nvidia-150b-taiwan-may-29: CoWoS customer allocation at 130k wafers/month target: Nvidia ~800-850k wafers/year (60%+); Broadcom ~240k wafers/year (primarily Google TPUs, Meta custom chips, OpenAI); AMD ~105k wafers/year (MI355/MI400). CoWoS-L and CoWoS-S remain fully booked through 2027 — no new capacity available for additional customers unless Nvidia releases allocation. GTC Taipei June 1, 2026 is next public milestone — watch for Vera Rubin shipment timeline and CoWoS-specific commentary.
Names and exposures
| Ticker | Exposure | Conviction |
|---|---|---|
| BESI | Bonder equipment for advanced packaging (CoWoS, flip-chip) | Medium-high — direct CoWoS tool play; less liquid than AMAT |
| AMAT | Advanced packaging tools; broad WFE portfolio | Already in picks-and-shovels; packaging is an incremental leg |
| ASE | Largest OSAT (outsourced semiconductor assembly/test); CoWoS sub-contractor | Medium — TSMC brings some CoWoS in-house, limiting ASE's share |
| AMKR | Amkor Technology — second-largest OSAT; HDFO independent CoWoS-equivalent (SWIFT/CoWoS-R, S-Connect/CoWoS-L); 5+ customers in qualification; AI packaging tripling in 2026 | Medium — graduation criteria met Q1 2026; $77 vs. original "cheaper entry" framing at lower price. See amkor |
Why this is picks-and-shovels rather than TSMC exposure
- TSMC captures the value of being the CoWoS provider — but TSMC is already richly valued and widely owned.
- Equipment makers (BESI, AMAT) and OSATs (ASE) see demand regardless of whether TSMC expands CoWoS in-house or licenses the process to partners.
- The bottleneck is multi-year: new CoWoS lines require 18–24 months of equipment delivery + qualification.
Contradictions / tensions
- If TSMC aggressively expands CoWoS capacity in-house faster than expected, BESI/ASE's relative exposure shrinks.
- AMAT already has exposure to this via its packaging segment, but that segment is a small fraction of AMAT's total WFE revenue — not a pure-play.
- AMD's MI300X and Google's TPUs also require CoWoS — the capacity crunch extends beyond Nvidia, but Nvidia dominates the current queue.
- A live no-CoWoS architecture exists. andrew-feldman in 2026-05-21-odd-lots-why-cerebras-ceo-andrew-feldman-built-the-world-s states cerebras's wafer-scale chip uses no CoWoS at all ("a process inside of TSMC called COAS... we don't use it"). The CoWoS crunch is a constraint on the GPU/chiplet architecture specifically; wafer-scale routes around it. As inference share grows and wafer-scale wins inference offtake (OpenAI $20B+, AWS), some demand may bypass the CoWoS bottleneck entirely — modestly capping the bottleneck's universality. See inference-demand-to-wafer-scale-advantage.
What would weaken this thesis
- AI training architectures shift to architectures that don't require CoWoS (e.g., disaggregated memory via CXL, optical I/O)
- TSMC dramatically accelerates CoWoS line additions, relieving the bottleneck in 2026–2027
Valuation snapshot
Last refreshed 2026-05-25. WebFetch unavailable (403) — price data not retrieved. BESI (Euronext Amsterdam), AMAT, ASE (NYSE) prices not available. Context: Nvidia consuming ~60% of total global CoWoS demand (595K wafers 2026); CoWoS sold through 2027 (50+ week lead times); TSMC outsourcing to ASE AND Amkor (15-20% persistent gap); AMKR exposure gap flagged — see amkor-cowos-tsmc-overflow-osat hypothesis.
| Ticker | Price | 52w range | Mkt cap | Fwd P/E | YTD | What's priced in (one line) |
|---|---|---|---|---|---|---|
| BESI | — | — | — | — | — | CoWoS bonder demand partially priced; Euronext liquidity limits US investor access |
| AMAT | — | — | — | — | — | See picks-and-shovels-leading-edge-fab-buildout — packaging is an incremental leg on top of WFE exposure |
| ASE | — | — | — | — | — | OSAT positioning priced; TSMC in-house CoWoS expansion limits ASE's addressable share gain |
Forward-looking outcomes (12-month)
Bull case — TSMC announces CoWoS expansion requiring 12–18 month equipment delivery; AMD/Broadcom join Nvidia in CoWoS capacity queuing; Intel's EMIB (90% yield) creates competitive demand for packaging equipment: BESI order book surges; AMAT packaging segment accelerates alongside WFE. Implied price: BESI +30–50%; ASE +20–30%. Cited: 2026-05-11-autoresearch-macro-semis-ai-infrastructure-may-2026, 2026-05-11-autoresearch-picks-shovels-semicap-update-may-2026.
Base case — CoWoS bottleneck persists through 2026; TSMC expands gradually; Nvidia maintains >50% CoWoS block; BESI/ASE demand steady: thesis valid but re-rating requires acceleration signal. Implied price: BESI +10–20%; ASE +5–15%. Cited: 2026-05-11-autoresearch-macro-semis-ai-infrastructure-may-2026.
Bear case — TSMC dramatically accelerates in-house CoWoS faster than 12–18 month equipment lead time suggests; CXL-based disaggregated memory reduces CoWoS demand from non-GPU chips: thesis weakens; BESI/ASE multiples compress; TSMC captures CoWoS value entirely in-house. Cited: cowos-packaging-capacity-crunch.md (contradictions section).
Currently undervalued vs base case? Research pending — BESI and ASE specific multiples not available. Conviction is medium-high but TSMC in-house expansion risk caps upside for ASE specifically.
Catalyst path:
- TSMC Q2 2026 earnings: explicit CoWoS capacity expansion announcement and equipment ordering signal
- AMD MI350/MI400 supply chain commentary: CoWoS allocation beyond Nvidia's 50% block
- Lam Research Vector Teos 3D first customer shipment: confirms competitive packaging tool market size