CoWoS packaging capacity crunch

One-line summary: Nvidia is consuming >50% of TSMC's total CoWoS (Chip-on-Wafer-on-Substrate) packaging capacity, creating a second supply bottleneck on top of the leading-edge logic foundry constraint — advanced packaging equipment makers (BESI, AMAT, ASE) benefit regardless of which GPU wins.

The insight

Leading-edge silicon is only part of the AI chip supply chain. After wafers are fabricated, HBM is bonded to logic dies through advanced packaging processes (CoWoS, SoIC, 3D stacking). Nvidia's GPU + HBM modules require CoWoS, and Nvidia's scale means it monopolizes TSMC's CoWoS capacity. This is an independent bottleneck from logic lithography and from raw HBM supply — it is the integration constraint.

Advanced packaging equipment is the picks-and-shovels play on this bottleneck: BESI (bonder equipment), AMAT (packaging tools), and ASE (OSAT assembly) all benefit as packaging capacity must expand.

The chain

TSMC CoWoS 50%+ consumed by Nvidia → AMD, Broadcom, Google TPU compete for remainder → packaging is the binding bottleneck for non-Nvidia accelerators; TSMC captures continued packaging revenue even as wafer fab is shared.

Canonical: hbm-cowos-as-binding-bottleneck.

Evidence

• From 2026-05-11-autoresearch-macro-semis-ai-infrastructure-may-2026: Nvidia consuming >50% of TSMC's total CoWoS capacity with 800–850K wafers/year. This level of concentration means any other customer needing CoWoS (AMD, Broadcom, others) faces a queue behind Nvidia.

• From 2026-05-11-autoresearch-picks-shovels-semicap-update-may-2026: Lam Research launched "Vector Teos 3D" to compete with AMAT in advanced packaging — the competitive entry confirms the market opportunity is large enough to attract a new tool entrant.

• From 2026-05-11-autoresearch-macro-semis-ai-infrastructure-may-2026: CoWoS backlog through 2026 is cited as a direct constraint on Nvidia shipment velocity — packaging, not just logic yield, is gating AI system delivery.

• From 2026-05-19-autoresearch-cowos-packaging-capacity-may-2026-update: TSMC May 14, 2026 Technology Symposium: CoWoS yield >98% on the 5.5-reticle-size CoWoS solution (largest chip-on-wafer ever produced at volume, supporting 12 HBM chips per package). Third-generation CoWoS volume production started 2026 (12 HBM stacks, up from 8).

• From 2026-05-19-autoresearch-cowos-packaging-capacity-may-2026-update: TSMC CoWoS target: 130,000 wafers/month by late 2026 (from ~35,000 WPM in late 2024 — nearly 4x in ~24 months). CoWoS + SoIC capacity CAGR: >80%/year through 2027. 5 new fabs coming online in 2026.

• From 2026-05-19-autoresearch-cowos-packaging-capacity-may-2026-update: Despite 4x capacity expansion, analysts expect only "slight easing" in supply-demand gap by 2027 — demand is growing at least as fast as supply. NVIDIA alone books ~60% of all CoWoS capacity (estimated 595,000 wafers in 2026), with advanced packaging lines booked "several years ahead."

• From 2026-05-19-autoresearch-cowos-packaging-capacity-may-2026-update: TSMC outsourcing to ASE and Amkor due to persistent 15-20% supply-demand gap — clearest signal TSMC cannot close the gap through internal expansion alone.

• From 2026-05-19-autoresearch-cowos-packaging-capacity-may-2026-update: BESI Q1 2026 results: revenue €184.9M (+28.3% YoY); orders €269.7M (more than doubled YoY, driven by hybrid bonding); backlog ~€400M; Q2 guidance +30-40% sequential (new record ~€240-260M); gross margin 64-66%. Needham named BESI Top Pick on HBM hybrid bonding thesis. 12-18 month lead times for hybrid bonders = Q1 orders → Q3-Q4 revenue.

• From 2026-05-19-autoresearch-cowos-packaging-capacity-may-2026-update: ASE Technology doubling advanced packaging sales to $3.2B in 2026; bought NT$2.8B Zhunan facility; serving NVIDIA, AMD, and others; projected to exceed 200,000 wafers by 2027; "likely to be primary beneficiary" of TSMC outsourcing.

• From 2026-05-19-autoresearch-cowos-packaging-capacity-may-2026-update: EMIB signal: TrendForce notes ASICs from hyperscalers are expected to shift from CoWoS to EMIB (Intel's Embedded Multi-die Interconnect Bridge). If Intel 18A packages with EMIB at scale, some ASIC demand could route around TSMC's CoWoS — simultaneously a mild headwind for CoWoS and a tailwind for the Intel thesis.

• From 2026-05-20-autoresearch-tsmc-capacity-pricing-power-n2-cowos-may-2026: CoWoS fully sold through 2027 per TSMC Q1 2026 earnings call (April 17, 2026). Management has aggressively built CoWoS capacity and packaging-focused fabs; Q2 2026 guidance implies continued strong CoWoS revenue contribution. 50+ week lead times as of Q1 2026.

• From 2026-05-25-autoresearch-tsmc-capacity-shortfall-may-2026-update: Nvidia securing ~60% of total global CoWoS demand (595K wafers booked 2026). TSMC outsourcing CoWoS steps to ASE AND Amkor Technology (AMKR) due to persistent 15-20% supply-demand gap.

• From 2026-05-26-autoresearch-amkr-cowos-advanced-packaging-q1-2026: AMKR Q1 2026 record $1.68B revenue (+27% YoY); AI advanced packaging guided to triple in 2026; HDFO platform (CoWoS-equivalent) has 5+ customers in qualification. Global CoWoS demand reaching ~1M wafers/year in 2026. Graduation criteria for amkor-cowos-tsmc-overflow-osat substantially met — AMKR added to suggested-tickers. Mechanism note: Amkor is both TSMC CoWoS overflow receiver AND independent HDFO platform vendor (SWIFT = CoWoS-R equivalent; S-Connect = CoWoS-L equivalent).

• From 2026-05-26-autoresearch-semis-ai-infra-macro-scan-may-23-26-2026: CoWoS ASP approaching $10,000/wafer — parity with 7nm advanced logic nodes (TrendForce, April 2026). TSMC CoWoS roadmap: current = 5.5-reticle-size; 2028 = 14-reticle-size CoWoS packages; 2029 = 48x compute leap, supporting 24 HBM5E stacks per package. This roadmap extends the packaging bottleneck thesis well beyond 2027 — each new generation requires new equipment investment. Nvidia Feynman (2028) expected to use HBM5, not HBM4.

• From 2026-05-29-autoresearch-cowos-nvidia-150b-taiwan-may-29: Nvidia $150B/year Taiwan pledge (announced Computex, May 27-28, 2026). Jensen Huang called Taiwan "the epicentre of the AI revolution." Nvidia Constellation Campus breaking ground June/July 2026, operations targeted 2030. During his Taiwan visit (May 23), Huang met TSMC Chairman C.C. Wei specifically to discuss Vera Rubin production commitments — the conversation was explicitly about packaging capacity for the next-generation platform.

• From 2026-05-29-autoresearch-cowos-nvidia-150b-taiwan-may-29: Vera Rubin six-die architecture adds fresh CoWoS demand. Vera Rubin is a six-chip multi-die system requiring more CoWoS interposer area per unit than GB300. TSMC must simultaneously ramp CoWoS for GB300 tail production while starting Vera Rubin front-end ramp — straining an already-oversubscribed line. Huang: Vera Rubin is "the most successful product generation in Nvidia's history" and "the biggest product ramp in computer history."

• From 2026-05-29-autoresearch-cowos-nvidia-150b-taiwan-may-29: CoWoS customer allocation at 130k wafers/month target: Nvidia ~800-850k wafers/year (60%+); Broadcom ~240k wafers/year (primarily Google TPUs, Meta custom chips, OpenAI); AMD ~105k wafers/year (MI355/MI400). CoWoS-L and CoWoS-S remain fully booked through 2027 — no new capacity available for additional customers unless Nvidia releases allocation. GTC Taipei June 1, 2026 is next public milestone — watch for Vera Rubin shipment timeline and CoWoS-specific commentary.

• From 2026-06-01-autoresearch-gtc-taipei-vera-rubin-macro-buckets: Vera Rubin supply chain confirmed 2× Blackwell — Jensen Huang, GTC Taipei June 1: "The supply chain for Vera Rubin is twice the size of what Blackwell required." Full production ramp by fall 2026. Vera Rubin uses a six-die architecture (NVL72: Rubin GPUs + Vera CPUs + Groq 3 LPX trays + Spectrum-6 networking + BlueField-4 storage). H2 2026 is now the confirmed CoWoS demand inflection point — supply chain twice Blackwell's with production starting this year.

• From 2026-06-01-autoresearch-gtc-taipei-vera-rubin-macro-buckets: Nvidia projects $1 trillion in cumulative Blackwell + Rubin orders by 2027. At 2× Blackwell supply chain scale and a $1T cumulative order book, the CoWoS throughput demand through 2027 is the largest in the packaging industry's history.

• From 2026-06-01-autoresearch-hbm-cowos-bottleneck-2026-corroboration: Independent (Morgan Stanley) confirmation of the ~60% Nvidia allocation: Nvidia ~60% of 2026 CoWoS (~595k wafers), AMD ~11% (~105k), Broadcom ~15% (150k, much of it Google TPU / Meta / OpenAI). TSMC doubling CoWoS ($56B capex; ~4× late-2024 by late 2026) but Nvidia's advanced-packaging lines are booked through 2027 — expansion is absorbed by demand, not easing the constraint. Corroborates the hbm-cowos-as-binding-bottleneck chain (step 2).

• ⬆ MU Q3 FY2026 print sustains the integration-demand premise (reported 2026-06-24) — the HBM that CoWoS bonds is now booked years out, so the downstream packaging demand has a multi-year floor. sumit-sadana in 2026-06-24-earnings-mu-q3-fy2026: "HBM3E and HBM4 are fully booked through calendar 2027, with demand extending into 2028"; "The demand continues to be well above our supply." mark-murphy in 2026-06-24-earnings-mu-q3-fy2026: HBM TAM "easily crossing $100 billion in 2027," pulled forward from the prior 2028 expectation, "underscoring sustained structural undersupply" (16 take-or-pay SCAs, ~$100B RPO, ~$22B deposits). Each HBM stack still has to be integrated onto a logic die — so the HBM lock-in through 2027 is a demand floor under the CoWoS/advanced-packaging crunch, reinforcing the canonical hbm-cowos-as-binding-bottleneck chain (step 2).

• ★★ The supplier itself says the bottleneck is capping its customers — first-party, unprompted, against interest (2026-07-17 ingest). cc-wei in 2026-07-16-earnings-tsm-q2-fy2026, asked how TSMC would react to Intel's EMIB-T gaining traction: "Well, let me say that our packaging capacity is so tight that now it's limiting my customers' growth. We welcome that additional flexibility in the market. That will help TSMC's front-end wafer business growth, which is a majority part of TSMC's business... Today, we're working very hard to shorten the gap between the demand and the capacity."

  Why this is the strongest evidence on this page. Every figure above is an analyst estimate, a research-shop allocation model, or an inference from a buyer's behavior. This is the monopolist supplier stating, on the record, that its own packaging capacity is the binding constraint on its customers' growth. A supplier has every incentive to claim its capacity is adequate; conceding that it is capping customer growth is a statement against interest, and it converts the CoWoS crunch from a modelled bottleneck into a disclosed one.

• ★ Wei welcomes Intel's EMIB-T as relief — which prices the bottleneck in lost revenue. cc-wei in 2026-07-16-earnings-tsm-q2-fy2026, asked whether back-end competition could become a gateway to front-end share loss: "The front end's wafer business and the back end's business are two different things... I also say that since our capacity in the back end is so in shortage mode, the gap is bigger. I welcome that the competitor offers some of the flexibility to my customer so that their front-end wafer can be put into the package, and that help TSMC's front-end wafer business. That's our attitude."

  This updates the EMIB signal logged from 2026-05-19-autoresearch-cowos-packaging-capacity-may-2026-update above, and it inverts the sign. The May read treated ASIC migration from CoWoS to EMIB as "a mild headwind for CoWoS and a tailwind for the Intel thesis." Wei's framing is that packaging scarcity is stranding TSMC's own front-end wafer revenue — so EMIB-T relief is net positive for TSM, because front-end wafer is "a majority part of TSMC's business" and packaging is the gate in front of it. The headwind read was too narrow: it priced the packaging revenue TSMC might lose and ignored the larger wafer revenue TSMC cannot currently bill. See tsmc-saturation-to-intel-anchor-stack.

• Advanced packaging still is not broken out, and Wei explains why — wendell-huang in 2026-07-16-earnings-tsm-q2-fy2026: "about 10%-20% will be spent for advanced packaging, testing, mask making, and others." Pressed by Evelyn Yu (Goldman) to separate packaging capex specifically, cc-wei declined and gave the reason: "we try very hard to make sure that our CapEx, the number is correct, with the flexibility between the front end and the back end. Sometimes we have a bottleneck, we put more money to buy the bottleneck tools, sometimes it's in the front end, sometimes it's in the back end." The fungibility is the point — TSMC deliberately keeps capex flexible to chase whichever end is binding, which is why an external CoWoS-capex figure does not exist.

• The glass-substrate alternative is ~1 year from production — cc-wei in 2026-07-16-earnings-tsm-q2-fy2026: "today, the majority is still CoWoS, right? We are developing that alternative, try to lower down the cost. We also work with a substrate vendor... we're building a pilot line that I announced a few quarters ago, and it will take about another one year to be mature so we can put it into the production with our customer." Confirms the 14x-reticle/glass roadmap above is real but not a 2026-27 relief valve.

• COUPE (co-packaged optics) is in production now — cc-wei in 2026-07-16-earnings-tsm-q2-fy2026: "We start the production right now, and it will be ramped up... the AI data center need to lower down the power consumption and increase the bandwidth of the communication channel. I believe the COUPE will continue to increase the demand, and then will become a very important technology in the next few years." A new advanced-packaging demand vector on top of CoWoS.

Names and exposures

Why this is picks-and-shovels rather than TSMC exposure

• TSMC captures the value of being the CoWoS provider — but TSMC is already richly valued and widely owned.
• Equipment makers (BESI, AMAT) and OSATs (ASE) see demand regardless of whether TSMC expands CoWoS in-house or licenses the process to partners.
• The bottleneck is multi-year: new CoWoS lines require 18–24 months of equipment delivery + qualification.

Contradictions / tensions

• If TSMC aggressively expands CoWoS capacity in-house faster than expected, BESI/ASE's relative exposure shrinks.
• AMAT already has exposure to this via its packaging segment, but that segment is a small fraction of AMAT's total WFE revenue — not a pure-play.
• AMD's MI300X and Google's TPUs also require CoWoS — the capacity crunch extends beyond Nvidia, but Nvidia dominates the current queue.
• A live no-CoWoS architecture exists. andrew-feldman in 2026-05-21-odd-lots-why-cerebras-ceo-andrew-feldman-built-the-world-s states cerebras's wafer-scale chip uses no CoWoS at all ("a process inside of TSMC called COAS... we don't use it"). The CoWoS crunch is a constraint on the GPU/chiplet architecture specifically; wafer-scale routes around it. As inference share grows and wafer-scale wins inference offtake (OpenAI $20B+, AWS), some demand may bypass the CoWoS bottleneck entirely — modestly capping the bottleneck's universality. See inference-demand-to-wafer-scale-advantage.

What would weaken this thesis

• AI training architectures shift to architectures that don't require CoWoS (e.g., disaggregated memory via CXL, optical I/O)
• TSMC dramatically accelerates CoWoS line additions, relieving the bottleneck in 2026–2027

Valuation snapshot

Last refreshed 2026-07-21 — TSM re-marked live to $402.30 (twelvedata, +0.99% intraday); the AMKR/ASE/BESI rows carry their 07-20 marks (AMKR not in the signal-instrument fetch set this run; ASE/BESI free-plan-gated). Every price fill tagged twelvedata. Mkt cap / Fwd P/E not in the free tier and not re-sourced for these names this run. Two of the four tickers on this page cannot be marked — see the stale rows below; this is a recurring free-plan limitation, not new breakage.

Forward-looking outcomes (12-month)

Bull case — the disclosed bottleneck converts to orders: cc-wei in 2026-07-16-earnings-tsm-q2-fy2026 stated first-party and unprompted that "our packaging capacity is so tight that now it's limiting my customers' growth" and that TSMC is "working very hard to shorten the gap between the demand and the capacity" — with capex raised to $60–64B (10–20% to advanced packaging, testing, mask making) plus advanced-packaging fabs inside the $100B Arizona commitment (wendell-huang, cc-wei, same source). Add COUPE co-packaged optics "in production right now" as a fresh demand vector. Overflow keeps routing to the OSATs on the persistent 15–20% gap (2026-05-25-autoresearch-tsmc-capacity-shortfall-may-2026-update); AMKR's AI advanced packaging triples in 2026 (2026-05-26-autoresearch-amkr-cowos-advanced-packaging-q1-2026). Implied price: AMKR back toward its $96.68 high (~+53%); BESI +30–50%; ASE +20–30%. Cited: 2026-07-16-earnings-tsm-q2-fy2026, 2026-05-11-autoresearch-macro-semis-ai-infrastructure-may-2026.

Base case — the bottleneck persists through 2026–27 and the OSATs earn through it without a re-rate: TSMC expands gradually, Nvidia holds its ~60% block, overflow volume to ASE/AMKR is steady. CoWoS-L and CoWoS-S remain fully booked through 2027 (2026-05-29-autoresearch-cowos-nvidia-150b-taiwan-may-29) and the glass-substrate alternative is "about another one year to be mature" per cc-wei in 2026-07-16-earnings-tsm-q2-fy2026 — so no relief valve arrives inside the window. Thesis valid; re-rating still requires an acceleration signal the tape isn't paying for. Implied price: AMKR +15–25%; BESI +10–20%; ASE +5–15%. Cited: 2026-05-11-autoresearch-macro-semis-ai-infrastructure-may-2026.

Bear case — TSMC accelerates in-house CoWoS faster than the 12–18 month equipment lead time suggests, capturing the value internally; CXL-based disaggregated memory reduces CoWoS demand from non-GPU chips; wafer-scale takes inference share and routes around CoWoS entirely — andrew-feldman in 2026-05-21-odd-lots-why-cerebras-ceo-andrew-feldman-built-the-world-s confirms cerebras uses no CoWoS at all. Thesis weakens; OSAT multiples compress from an already-de-rated base. Implied price: AMKR −25–35%. Cited: cowos-packaging-capacity-crunch.md (contradictions section), inference-demand-to-wafer-scale-advantage.

Currently undervalued vs base case? AMKR: Yes — changed from "Research pending," and the day's move is why. The prior answer deferred on the grounds that BESI/ASE multiples were unavailable; that dodge is no longer necessary, because the page's one liquid, markable name just fell 6.8% to −34.8% from its high on the same day the monopolist supplier confirmed the bottleneck AMKR exists to absorb. That is a widening gap between price and thesis, not a thesis deterioration. ⚠ Two honest limits: (1) this is a distance-from-high and first-party-evidence argument, not a multiple-based valuation — no forward P/E for AMKR was sourced this run; (2) Wei's welcome of Intel's EMIB-T as relief is double-edged for the OSATs — it means packaging demand may route to a competitor's bridge rather than to CoWoS overflow. BESI / ASE: unchanged — Research pending, and now compounded by the fact that neither can even be price-marked on the free tier (stale since 2026-07-15). TSMC in-house expansion risk still caps ASE specifically.

Catalyst path:

• AMKR Q2 2026 earnings (early August) — does the "AI advanced packaging triples in 2026" guide hold, and do the 5+ HDFO qualification customers convert? The nearest gate, and the one that tests the −34.8% de-rate directly.
• TSMC Q3 2026 earnings (October) — Wei said the packaging gap is "bigger" than the front-end gap; watch whether he still says packaging is limiting customer growth after a quarter of $60–64B-capex spending.
• A named EMIB-T customer at Intel — would confirm Wei's "welcome the flexibility" framing is real demand routing, and is the cleanest near-term falsifier for the CoWoS-overflow leg. See us-fab-capacity-bottleneck.

Related

• hbm-supply-bottleneck
• picks-and-shovels-leading-edge-fab-buildout
• tsmc-capacity-shortfall-and-pricing-power
• tsmc
• hbm-cowos-as-binding-bottleneck
• cerebras
• inference-demand-to-wafer-scale-advantage